Design of a 4-bit absolute-value detector based on CMOS&PTL

• Main Authors: Sun, Yimeng, Wang, Yucheng, Yu, Feiyang
• Format: Conference Proceeding
• Language: English
• Subjects: CMOS; Critical path; Delay; Design parameters; Energy consumption; Integrated circuits; Mathematical analysis; Transistor logic
• ISSN: 0094-243X; 1551-7616
• DOI: 10.1063/5.0173848

Powered by advanced information technology, integrated circuits have been widely involved in various fields. The detection and processing of electrical signals has become one of the important steps. This paper designs a 4-bit absolute value detector using CMOS logic and Pass-Transistor Logic (PTL). It can compare the input binary number with the set threshold, which can detect the peak signal to reduce the interference of noise and improve the detection accuracy of the signal. This paper innovatively uses the full adder to design the absolute value detection part, which can reduce the number of CMOS and reduce energy consumption. To increase driving strength and improve logic delay, the design uses a two-inverter chain as a buffer. To achieve the goal of low energy consumption and low delay, this paper calculates the minimum delay case based on the theory of logic effort and the critical path of the circuit. Through comparing only sizing, only voltage scaling and combining method, the final minimum energy consumption is calculated. The parameters for this design are 12.74 FO4 (0.933V) and 9.58 Eu (0.933V). This means that it can improve the reliability of the device and improve the signal response speed in practical applications.