SiC Trench MOSFET with Depletion-Mode pMOS for Enhanced Short-Circuit Capability and Switching Performance

A novel 4H-SiC trench metal-oxide-semiconductor field-effect transistor (TMOS) with depletion-mode pMOS (D-pMOS) is proposed and investigated via TCAD simulation. It has an auxiliary gate electrode that controls the electrical connections of P-shield layers under the trench bottom through the D-pMOS...

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Bibliographic Details
Published in:Electronics (Basel) 2023-12, Vol.12 (23), p.4764
Main Authors: Yu, Hengyu, Shi, Limeng, Bhattacharya, Monikuntala, Jin, Michael, Qian, Jiashu, Agarwal, Anant K.
Format: Article
Language:English
Subjects:
Circuit design
Depletion
Design and construction
Electric fields
Electrodes
Field effect transistors
Integrated circuit fabrication
JFET
Materials
Metal oxide semiconductor field effect transistors
Metal oxide semiconductors
Methods
MOSFETs
Semiconductor devices
Short circuits
Silicon carbide
Simulation
Switching
Transistors
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Summary:A novel 4H-SiC trench metal-oxide-semiconductor field-effect transistor (TMOS) with depletion-mode pMOS (D-pMOS) is proposed and investigated via TCAD simulation. It has an auxiliary gate electrode that controls the electrical connections of P-shield layers under the trench bottom through the D-pMOS. In linear operation, the D-pMOS is turned off and then the potential of the P-shield layers is raised with the auxiliary gate, which shrinks the width of the depletion region of the P-shield/N-drift junction to reduce the resistance of the JFET region. In the saturation operation, the saturation current density of the proposed TMOS is reduced, benefiting from its relatively large cell pitch. The design concept eases the tension between specific on-resistance and short circuit capabilities. Numerical simulation results show that the proposed TMOS exhibits a short circuit withstand time that is 1.92 times longer than that of the conventional TMOS. In addition, a drive tactic is introduced and optimized for the proposed TMOS, which requires only one set of gate drivers. Compared with the conventional TMOS, the switching performance is improved and the switching loss is reduced by 40%.
ISSN:2079-9292
2079-9292
DOI:10.3390/electronics12234764