A Capacitively-Coupled Chopper Instrumentation Amplifier with Compensated Auto-Zeroed DC Servo-Loop for Neural signal Recording

• Published in: IEEE transactions on circuits and systems. II, Express briefs Express briefs, 2023-12, Vol.70 (12), p.1-1
• Main Authors: Zhou, Zhijun, Zhu, Longbin, Wang, Wenjie, Li, Jihong, Meng, Qiao, Wang, Zhigong
• Format: Article
• Language: English
• Subjects: Analog integrated circuits; biomedical monitoring; Capacitors; Choppers (circuits); Circuit design; Clocks; CMOS integrated circuits; dc servo loop; DSL; Frequencies; Instruments; Integrated circuits; Integrators; noise cancellation; Power consumption; Recording; Servoamplifiers; switched capacitor circuits; Switches; Timing
• ISSN: 1549-7747; 1558-3791
• DOI: 10.1109/TCSII.2023.3291375

This paper presents a capacitively-coupled chopper instrumentation amplifier (CCIA) with a compensated autozeroed (CAZ) dc servo-loop (DSL) for neural signal recording. The proposed CAZ technique samples the low-frequency feedthrough noise via the DSL that appears at the output of CCIA, and compensates it in the integrating phase of a switched-capacitor (SC) based integrator. The proposed CAZ DSL provides circa 36% lower input-referred noise (IRN) than conventional SC integrator DSL, without the need for an extra timing phase. Circuits are targeted at integrated circuit implementation and designed using a 0.18 μm CMOS technology. The proposed CCIA provides a circa 41.5 dB mid-band gain, consumes a power of 4 μW and has a die area of 0.24 mm2. It achieves an IRN of 0.73 μVrms in the local field potential frequency band and 2.86 μVrms for the action potential frequency band.