VLSI implementation of vedic multiplier and carry look ahead adder based FIR filter for denoising EEG signal

• Main Authors: Pavithara, P., Devi, P. Nirmala, Pavithra, M., Dharani, L. R., Akshaya, M., Deepthi, S.
• Format: Conference Proceeding
• Language: English
• Subjects: Adding circuits; Design; Electroencephalography; FIR filters; Frequency ranges; Multiplication; Multipliers; Noise reduction; Resource utilization; Signal processing
• ISSN: 0094-243X; 1551-7616
• DOI: 10.1063/5.0178693

Finite Impulse Response filters have been used recently for signal processing applications. Denoising signals with an effective multiplier design is one of the most common applications of signal processing. The FIR filter approach for denoising the Electroencephalogram (EEG) signal uses a vedic multiplier and carry lookahead adder based architecture. Vedic multiplier and carry lookahead adder based FIR filter is designed to effectively denoise the EEG signal. The vedic multiplier design is used for the fastest multiplication process. The carry lookahead adder proposed eliminates the propagation delay factor and performs effective addition process. The EEG signal obtained from Bonn University of Germany is utilized. The preprocessing stage involves filtering of EEG signal to remove noise. The frequency range of human brain signal ranges from 0 to 60Hz which is captured by EEG. The signals above 60 Hz include noise and those frequencies are removed by proposed Finite Impulse Response filter with a cut off frequency of 60Hz. The FFT of denoised signal is performed to verify the effectiveness of designed filter and it is observed that all the frequencies above 60Hz are removed. The FPGA implementation is performed and resource utilization report is analyzed.