Gemini: Mapping and Architecture Co-exploration for Large-scale DNN Chiplet Accelerators

Chiplet technology enables the integration of an increasing number of transistors on a single accelerator with higher yield in the post-Moore era, addressing the immense computational demands arising from rapid AI advancements. However, it also introduces more expensive packaging costs and costly Di...

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Published in:arXiv.org 2023-12
Main Authors: Cai, Jingwei, Wu, Zuotong, Sen, Peng, Wei, Yuchen, Tan, Zhanhong, Shi, Guiming, Gao, Mingyu, Ma, Kaisheng
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Accelerators
Mapping
Power consumption
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Wu, Zuotong
Sen, Peng
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Tan, Zhanhong
Shi, Guiming
Gao, Mingyu
Ma, Kaisheng
description Chiplet technology enables the integration of an increasing number of transistors on a single accelerator with higher yield in the post-Moore era, addressing the immense computational demands arising from rapid AI advancements. However, it also introduces more expensive packaging costs and costly Die-to-Die (D2D) interfaces, which require more area, consume higher power, and offer lower bandwidth than on-chip interconnects. Maximizing the benefits and minimizing the drawbacks of chiplet technology is crucial for developing large-scale DNN chiplet accelerators, which poses challenges to both architecture and mapping. Despite its importance in the post-Moore era, methods to address these challenges remain scarce.
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subjects Accelerators
Mapping
Power consumption
title Gemini: Mapping and Architecture Co-exploration for Large-scale DNN Chiplet Accelerators
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