In-ADC, Rank-Order Filter for Digital Pixel Sensors

This paper presents a new implementation of the rank-order filter, which is established on a parallel-operated array of single-slope (SS) analog-to-digital converters (ADCs). The SS ADCs use an “on-the-ramp processing” technique, i.e., filtration is performed along with analog-to-digital conversion,...

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Bibliographic Details
Published in:Electronics (Basel) 2024-01, Vol.13 (1), p.46
Main Authors: Kłosowski, Miron, Sun, Yichuang, Jendernalik, Waldemar, Blakiewicz, Grzegorz, Jakusz, Jacek, Szczepański, Stanisław
Format: Article
Language:English
Subjects:
Analog to digital conversion
Analog to digital converters
Arrays
Digitization
Energy efficiency
Frames per second
Image acquisition
Image filters
Neighborhoods
Power consumption
Sampling
Sensors
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Summary:This paper presents a new implementation of the rank-order filter, which is established on a parallel-operated array of single-slope (SS) analog-to-digital converters (ADCs). The SS ADCs use an “on-the-ramp processing” technique, i.e., filtration is performed along with analog-to-digital conversion, so the final states of the converters represent a filtered image. A proof-of-concept 64 × 64 array of SS ADCs, integrated with MOS photogates, was fabricated using a standard 180 nm CMOS process. The measurement results demonstrate the full functionality of the novel filter concept, with image acquisition in both single-sampling and correlated-double-sampling (CDS) modes (CDS is digitally performed using ADCs). The experimental, massively parallel rank-order filter can process 650 frames per second with a power consumption of 4.81 mW.
ISSN:2079-9292
2079-9292
DOI:10.3390/electronics13010046