Modeling and analysis of gate-induced drain leakage current in negative capacitance junctionless FinFET

The gate-induced drain leakage (GIDL) current is one of the important short channel effects. It is very significant to study the GIDL current ( I GIDL ) in negative capacitance-based FETs as the additional ferroelectric layer affects the electric field as well as band-to-band tunneling. This article...

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Bibliographic Details
Published in:Journal of computational electronics 2022-12, Vol.21 (6), p.1229-1238
Main Authors: Kaushal, Shelja, Rana, Ashwani K.
Format: Article
Language:English
Subjects:
Capacitance
CMOS
Design
Electric fields
Electrical Engineering
Electrons
Engineering
Ferroelectric materials
Ferroelectricity
Leakage current
Mathematical and Computational Engineering
Mathematical and Computational Physics
Mathematical models
Mechanical Engineering
Optical and Electronic Materials
Physical properties
Semiconductors
Theoretical
Thickness
Transistors
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Summary:The gate-induced drain leakage (GIDL) current is one of the important short channel effects. It is very significant to study the GIDL current ( I GIDL ) in negative capacitance-based FETs as the additional ferroelectric layer affects the electric field as well as band-to-band tunneling. This article proposed an analytical model for GIDL current in negative capacitance junctionless FinFET (NC-JL FinFET). This model is based on tunneling mechanism and the impact of the negative capacitance is taken into consideration through LK equation. Further, the influence of various physical parameters like ferroelectric thickness, fin thickness, fin height, etc. on I GIDL of NC-JL FinFET has been also examined. It is determined that the thinner ferroelectric layer as well as fin will provide better I GIDL . It has been found that this model is computationally efficient and easy to realize, and the clearly verified results emphasize its accuracy.
ISSN:1569-8025
1572-8137
DOI:10.1007/s10825-022-01930-9