Designing digital circuits using 3D nanomagnetic logic architectures

• Published in: Journal of computational electronics 2021-06, Vol.20 (3), p.1310-1325
• Main Authors: Bhoi, Bandan Kumar, Pathak, Nirupma, Kumar, Santosh, Misra, Neeraj Kumar
• Format: Article
• Language: English
• Subjects: Arithmetic and logic units; Circuit design; Circuits; Design; Digital electronics; Electrical Engineering; Engineering; Error correction & detection; Leakage current; Logic; Mathematical and Computational Engineering; Mathematical and Computational Physics; Mechanical Engineering; Metal oxide semiconductors; Nanoelectronics; Optical and Electronic Materials; Parity; Performance degradation; Theoretical; Transistors; Voters
• ISSN: 1569-8025; 1572-8137
• DOI: 10.1007/s10825-020-01647-7

The approach to designing digital circuits using three-dimensional (3D) perpendicular nanomagnetic logic (pNML) is thoroughly investigated. Nanomagnetic logic (NML) technology eventually optimizes the circuit performance in comparison with conventional metal–oxide–semiconductor (MOS) technology, which suffers from the hot carrier, velocity saturation, and short-channel effects, which may considerably degrade device performance. In contrast, nanomagnetic logic is immune to radiation; it behaves as nonvolatile memory and shows zero leakage current, as required for use in high-speed and low-cost nanoelectronics applications. In this paper, novel and organized designs, e.g., for 3D Ex-OR, parity generator, parity checker, multiplexer, and arithmetic logic unit (ALU) functionality, are synthesized using pNML technology. Previous designs are not compact in terms of delay, layer count, or bounded area. To overcome this, new designs for the mentioned functionalities are proposed based on pNML with smaller area and lower latency compared with previous circuits.