Junctionless FETs based on a silicon-on-insulator architecture with a buried metal fin for multi-threshold operation

• Published in: Journal of computational electronics 2022-12, Vol.21 (6), p.1250-1261
• Main Authors: Singh, Dipak Kumar, Nagar, Bal Chand, Akram, M. W.
• Format: Article
• Language: English
• Subjects: Calibration; Electric fields; Electrical Engineering; Engineering; Mathematical and Computational Engineering; Mathematical and Computational Physics; Mechanical Engineering; Optical and Electronic Materials; Silicon; Simulation; SOI (semiconductors); Theoretical; Threshold voltage; Work functions
• ISSN: 1569-8025; 1572-8137
• DOI: 10.1007/s10825-022-01948-z

In this paper, an n-channel junctionless FinFET (JL FinFET) based on a silicon-on-insulator (SOI) architecture with a buried metal fin (BMF) is presented. We show that the BMF with a suitable work function of the proposed BMF-SOI-JL FinFET device can control the channel electrostatic field by employing a Schottky junction effectively. The enhanced association of potential between BMF and the channel combined with gate electric field makes it worthy for multi-threshold and dynamic threshold (DT) operation. Additionally, the biasing of the BMF projects the broad range of threshold voltage ( V TH ) regulation with a high value of body factor ( γ ). The proposed device demonstrates γ enhancement compared to a fin body (FB)-JL FET and conventional SOI-JL FinFETs under identical conditions due to constant potential coupling. The DT mode of operation shows a 73% improvement in ON-state current in addition to reduced subthreshold swing contrast to a BMF-SOI-JL FinFET without DT. This paper imparts a viable option for low-power applications with multi-threshold operation and high switching speed applications with DT operation.