A Comprehensive Review on the Single Gate, Double Gate, Tri-Gate, and Heterojunction Tunnel FET for Future Generation Devices

• Published in: SILICON 2023-04, Vol.15 (5), p.2385-2405
• Main Authors: Hannah Blessy, P., Shenbagavalli, A., Arun Samuel, T. S.
• Format: Article
• Language: English
• Subjects: Chemistry; Chemistry and Materials Science; CMOS; Design; Engineering; Environmental Chemistry; Field effect transistors; Heterojunctions; Hot electrons; Inorganic Chemistry; Lasers; Leakage current; Materials Science; MOSFETs; Nanoelectronics; Nanotechnology devices; Optical Devices; Optics; Photonics; Polymer Sciences; Power consumption; Power management; Review Paper; Silicon; Threshold voltage; Transistors; Tunnels
• ISSN: 1876-990X; 1876-9918
• DOI: 10.1007/s12633-022-02189-2

Today’s generation of the technological world needs low-power application devices and low-cost transistors. Recently researchers have developed a 3 nm MOSFET nanoelectronics device. Even though MOSFET reduces its size and power consumption, it prompts a few issues due to SCEs such as Hot electron, leakage current, threshold voltage roll-off, Impact Ionization, Drain Induced Barrier lowering (DIBL), and so on. The tunnel FET (TFET) structure is one of the best-proposed structures instead of the MOSFET structure, and it overcomes the limits induced by the CMOS transistor. TFET structure is very suitable for low-power applications. TFET structure breaks the limits of CMOS’s subthreshold swing and attains an average subthreshold swing of 60 mv/decade at normal temperature. The investigation of various TFET structure designs is the emphasis of this work. This study discusses the numerous suggested TFET architectures, such as Heterojunction TFET, Double Gate TFET, Tri-Gate TFET, and Single Gate TFET, and their performance.