Optimization of Design Space Parameters in Tunnel Fet for Analog/Mixed Signal Application

The investigation of TFET for analog and RF application thus far is least focused. This paper presents an extensive investigation of TFET design space parameters on analog performance, and the study is more application perspective. The considered design space parameter is gate length. The impact of...

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Bibliographic Details
Published in:SILICON 2022-08, Vol.14 (13), p.8233-8241
Main Authors: Jeyanthi, J. E., Samuel, T. S. Arun, Arivazhagan, L.
Format: Article
Language:English
Subjects:
Bandwidths
Business metrics
CAD
Chemistry
Chemistry and Materials Science
Computer aided design
Design
Design optimization
Design parameters
Digital signal processors
Efficiency
Environmental Chemistry
Inorganic Chemistry
Investigations
Lasers
Materials Science
Optical Devices
Optics
Optimization
Original Paper
Photonics
Physics
Polymer Sciences
Random access memory
Signal processing
Simulation
Transconductance
Transistors
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Summary:The investigation of TFET for analog and RF application thus far is least focused. This paper presents an extensive investigation of TFET design space parameters on analog performance, and the study is more application perspective. The considered design space parameter is gate length. The impact of gate length on TFET performance is investigated using Technology Computer-Aided Design (TCAD) physical simulator. In this work, new observations have been made on cut-off frequency (fT) and gain-bandwidth product (fM). For lower gate length, transconductance is the predominant mechanism for the reduction of fT and fM. For higher gate length, gate-to-drain capacitance (C gd ) is the predominant mechanism for reducing fT and fM. Further, the lower gate length is not optimal for transconductance efficiency, while the higher gate length is not optimal for switching loss. The investigation in this paper shown that TFET with gate length of 10 nm to 20 nm has proved to be an optimal candidate for analog and RF application. It is the first time suggestion on the selection of TFET gate length for analog application.
ISSN:1876-990X
1876-9918
DOI:10.1007/s12633-021-01591-6