Junctionless Gate-all-around Nanowire FET with Asymmetric Spacer for Continued Scaling

• Published in: SILICON 2022-08, Vol.14 (13), p.7461-7471
• Main Authors: Sreenivasulu, V. Bharath, Narendar, Vadthiya
• Format: Article
• Language: English
• Subjects: Asymmetry; Chemistry; Chemistry and Materials Science; Dielectrics; Electrical properties; Environmental Chemistry; Hafnium oxide; Inorganic Chemistry; Lasers; Materials Science; Nanowires; Optical Devices; Optics; Original Paper; Photonics; Polymer Sciences; Power consumption; Power management; Scaling; Silicon dioxide; Silicon nitride; Transconductance
• ISSN: 1876-990X; 1876-9918
• DOI: 10.1007/s12633-021-01471-z

In this paper, we have performed the scaling of asymmetric junctionless (JL) SOI nanowire (NW) FET at 10 nm gate length ( L G ). To study the device electrical performance various DC metrics like SS, DIBL, I ON / I OFF ratio are discussed. Even at 5 nm, the device has good electrical properties with subthreshold swing (SS) = ~64 mV/dec, drain induced barrier lowering (DIBL) = ~45 mV/V, and switching ratio ( I ON / I OFF ) = ~10 6 shows a higher level of electrostatic integrity. At 5 nm L G with optimized spacer dielectric the device exhibits ~5 orders of improvement in I OFF and the improvement is less than ~2 orders at 20 nm L G . Thus, from the result analysis, the spacer dielectrics are essential at lower L G for better performance. For continued scaling, the HfO 2 spacer dielectric ensures high performance with the lowest downfall in I ON with 11.24% and the decline is 15.8% and 13.26% with no spacer and Si 3 N 4 respectively. With SiO 2 , Si 3 N 4 , and HfO 2 spacers the asymmetric spacer ensures an I ON / I OFF of ~10 6 which is permissible for ITRS low power requirements. Moreover, to study scaling flexibility towards analog/RF applications various parameters like transconductance ( g m ), transconductance generation factor (TGF), total gate capacitance ( C gg ), and cutoff frequency ( f T ) are also determined. Furthermore, the scaling impact on dynamic power (DP) and static power (SP) consumption are also presented. The findings of the study show that asymmetric JL NW FET is one of the potential candidates for future technology nodes.