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Junctionless Gate-all-around Nanowire FET with Asymmetric Spacer for Continued Scaling
In this paper, we have performed the scaling of asymmetric junctionless (JL) SOI nanowire (NW) FET at 10 nm gate length ( L G ). To study the device electrical performance various DC metrics like SS, DIBL, I ON / I OFF ratio are discussed. Even at 5 nm, the device has good electrical properties with...
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Published in: | SILICON 2022-08, Vol.14 (13), p.7461-7471 |
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creator | Sreenivasulu, V. Bharath Narendar, Vadthiya |
description | In this paper, we have performed the scaling of asymmetric junctionless (JL) SOI nanowire (NW) FET at 10 nm gate length (
L
G
). To study the device electrical performance various DC metrics like SS, DIBL,
I
ON
/
I
OFF
ratio are discussed. Even at 5 nm, the device has good electrical properties with subthreshold swing (SS) = ~64 mV/dec, drain induced barrier lowering (DIBL) = ~45 mV/V, and switching ratio (
I
ON
/
I
OFF
) = ~10
6
shows a higher level of electrostatic integrity. At 5 nm
L
G
with optimized spacer dielectric the device exhibits ~5 orders of improvement in
I
OFF
and the improvement is less than ~2 orders at 20 nm
L
G
. Thus, from the result analysis, the spacer dielectrics are essential at lower
L
G
for better performance. For continued scaling, the HfO
2
spacer dielectric ensures high performance with the lowest downfall in
I
ON
with 11.24% and the decline is 15.8% and 13.26% with no spacer and Si
3
N
4
respectively. With SiO
2
, Si
3
N
4
, and HfO
2
spacers the asymmetric spacer ensures an
I
ON
/
I
OFF
of ~10
6
which is permissible for ITRS low power requirements. Moreover, to study scaling flexibility towards analog/RF applications various parameters like transconductance (
g
m
), transconductance generation factor (TGF), total gate capacitance (
C
gg
), and cutoff frequency (
f
T
) are also determined. Furthermore, the scaling impact on dynamic power (DP) and static power (SP) consumption are also presented. The findings of the study show that asymmetric JL NW FET is one of the potential candidates for future technology nodes. |
doi_str_mv | 10.1007/s12633-021-01471-z |
format | article |
fullrecord | <record><control><sourceid>proquest_cross</sourceid><recordid>TN_cdi_proquest_journals_2919455240</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>2919455240</sourcerecordid><originalsourceid>FETCH-LOGICAL-c363t-faf37e8e152c8ad16eec045832958036217c4556b304023a659b2d2d3e787c723</originalsourceid><addsrcrecordid>eNp9kM1KAzEURoMoWLQv4CrgOpqfmSSzLEWrUnRRFXchzWTqlGlSkwylfXqjI7rzbu5dfOe7cAC4IPiKYCyuI6GcMYQpQZgUgqDDERgRKTiqKiKPf2_8dgrGMa5xHkaF5NUIvD70zqTWu87GCGc6WaS7Dunge1fDR-38rg0W3t48w12b3uEk7jcbm0Jr4GKrjQ2w8QFOvUut620NF0Z3rVudg5NGd9GOf_YZeMkV0zs0f5rdTydzZBhnCTW6YcJKS0pqpK4Jt9bgopSMVqXEjFMiTFGWfMlwgSnTvKyWtKY1s0IKIyg7A5dD7zb4j97GpNa-Dy6_VLQiVWZpgXOKDikTfIzBNmob2o0Oe0Ww-lKoBoUqK1TfCtUhQ2yAYg67lQ1_1f9Qn_fYc2Y</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>2919455240</pqid></control><display><type>article</type><title>Junctionless Gate-all-around Nanowire FET with Asymmetric Spacer for Continued Scaling</title><source>Springer Nature</source><creator>Sreenivasulu, V. Bharath ; Narendar, Vadthiya</creator><creatorcontrib>Sreenivasulu, V. Bharath ; Narendar, Vadthiya</creatorcontrib><description>In this paper, we have performed the scaling of asymmetric junctionless (JL) SOI nanowire (NW) FET at 10 nm gate length (
L
G
). To study the device electrical performance various DC metrics like SS, DIBL,
I
ON
/
I
OFF
ratio are discussed. Even at 5 nm, the device has good electrical properties with subthreshold swing (SS) = ~64 mV/dec, drain induced barrier lowering (DIBL) = ~45 mV/V, and switching ratio (
I
ON
/
I
OFF
) = ~10
6
shows a higher level of electrostatic integrity. At 5 nm
L
G
with optimized spacer dielectric the device exhibits ~5 orders of improvement in
I
OFF
and the improvement is less than ~2 orders at 20 nm
L
G
. Thus, from the result analysis, the spacer dielectrics are essential at lower
L
G
for better performance. For continued scaling, the HfO
2
spacer dielectric ensures high performance with the lowest downfall in
I
ON
with 11.24% and the decline is 15.8% and 13.26% with no spacer and Si
3
N
4
respectively. With SiO
2
, Si
3
N
4
, and HfO
2
spacers the asymmetric spacer ensures an
I
ON
/
I
OFF
of ~10
6
which is permissible for ITRS low power requirements. Moreover, to study scaling flexibility towards analog/RF applications various parameters like transconductance (
g
m
), transconductance generation factor (TGF), total gate capacitance (
C
gg
), and cutoff frequency (
f
T
) are also determined. Furthermore, the scaling impact on dynamic power (DP) and static power (SP) consumption are also presented. The findings of the study show that asymmetric JL NW FET is one of the potential candidates for future technology nodes.</description><identifier>ISSN: 1876-990X</identifier><identifier>EISSN: 1876-9918</identifier><identifier>DOI: 10.1007/s12633-021-01471-z</identifier><language>eng</language><publisher>Dordrecht: Springer Netherlands</publisher><subject>Asymmetry ; Chemistry ; Chemistry and Materials Science ; Dielectrics ; Electrical properties ; Environmental Chemistry ; Hafnium oxide ; Inorganic Chemistry ; Lasers ; Materials Science ; Nanowires ; Optical Devices ; Optics ; Original Paper ; Photonics ; Polymer Sciences ; Power consumption ; Power management ; Scaling ; Silicon dioxide ; Silicon nitride ; Transconductance</subject><ispartof>SILICON, 2022-08, Vol.14 (13), p.7461-7471</ispartof><rights>Springer Nature B.V. 2021</rights><rights>Springer Nature B.V. 2021.</rights><lds50>peer_reviewed</lds50><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c363t-faf37e8e152c8ad16eec045832958036217c4556b304023a659b2d2d3e787c723</citedby><cites>FETCH-LOGICAL-c363t-faf37e8e152c8ad16eec045832958036217c4556b304023a659b2d2d3e787c723</cites><orcidid>0000-0003-3064-1522</orcidid></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><link.rule.ids>314,780,784,27924,27925</link.rule.ids></links><search><creatorcontrib>Sreenivasulu, V. Bharath</creatorcontrib><creatorcontrib>Narendar, Vadthiya</creatorcontrib><title>Junctionless Gate-all-around Nanowire FET with Asymmetric Spacer for Continued Scaling</title><title>SILICON</title><addtitle>Silicon</addtitle><description>In this paper, we have performed the scaling of asymmetric junctionless (JL) SOI nanowire (NW) FET at 10 nm gate length (
L
G
). To study the device electrical performance various DC metrics like SS, DIBL,
I
ON
/
I
OFF
ratio are discussed. Even at 5 nm, the device has good electrical properties with subthreshold swing (SS) = ~64 mV/dec, drain induced barrier lowering (DIBL) = ~45 mV/V, and switching ratio (
I
ON
/
I
OFF
) = ~10
6
shows a higher level of electrostatic integrity. At 5 nm
L
G
with optimized spacer dielectric the device exhibits ~5 orders of improvement in
I
OFF
and the improvement is less than ~2 orders at 20 nm
L
G
. Thus, from the result analysis, the spacer dielectrics are essential at lower
L
G
for better performance. For continued scaling, the HfO
2
spacer dielectric ensures high performance with the lowest downfall in
I
ON
with 11.24% and the decline is 15.8% and 13.26% with no spacer and Si
3
N
4
respectively. With SiO
2
, Si
3
N
4
, and HfO
2
spacers the asymmetric spacer ensures an
I
ON
/
I
OFF
of ~10
6
which is permissible for ITRS low power requirements. Moreover, to study scaling flexibility towards analog/RF applications various parameters like transconductance (
g
m
), transconductance generation factor (TGF), total gate capacitance (
C
gg
), and cutoff frequency (
f
T
) are also determined. Furthermore, the scaling impact on dynamic power (DP) and static power (SP) consumption are also presented. The findings of the study show that asymmetric JL NW FET is one of the potential candidates for future technology nodes.</description><subject>Asymmetry</subject><subject>Chemistry</subject><subject>Chemistry and Materials Science</subject><subject>Dielectrics</subject><subject>Electrical properties</subject><subject>Environmental Chemistry</subject><subject>Hafnium oxide</subject><subject>Inorganic Chemistry</subject><subject>Lasers</subject><subject>Materials Science</subject><subject>Nanowires</subject><subject>Optical Devices</subject><subject>Optics</subject><subject>Original Paper</subject><subject>Photonics</subject><subject>Polymer Sciences</subject><subject>Power consumption</subject><subject>Power management</subject><subject>Scaling</subject><subject>Silicon dioxide</subject><subject>Silicon nitride</subject><subject>Transconductance</subject><issn>1876-990X</issn><issn>1876-9918</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2022</creationdate><recordtype>article</recordtype><recordid>eNp9kM1KAzEURoMoWLQv4CrgOpqfmSSzLEWrUnRRFXchzWTqlGlSkwylfXqjI7rzbu5dfOe7cAC4IPiKYCyuI6GcMYQpQZgUgqDDERgRKTiqKiKPf2_8dgrGMa5xHkaF5NUIvD70zqTWu87GCGc6WaS7Dunge1fDR-38rg0W3t48w12b3uEk7jcbm0Jr4GKrjQ2w8QFOvUut620NF0Z3rVudg5NGd9GOf_YZeMkV0zs0f5rdTydzZBhnCTW6YcJKS0pqpK4Jt9bgopSMVqXEjFMiTFGWfMlwgSnTvKyWtKY1s0IKIyg7A5dD7zb4j97GpNa-Dy6_VLQiVWZpgXOKDikTfIzBNmob2o0Oe0Ww-lKoBoUqK1TfCtUhQ2yAYg67lQ1_1f9Qn_fYc2Y</recordid><startdate>20220801</startdate><enddate>20220801</enddate><creator>Sreenivasulu, V. Bharath</creator><creator>Narendar, Vadthiya</creator><general>Springer Netherlands</general><general>Springer Nature B.V</general><scope>AAYXX</scope><scope>CITATION</scope><scope>8FE</scope><scope>8FG</scope><scope>ABJCF</scope><scope>AFKRA</scope><scope>BENPR</scope><scope>BGLVJ</scope><scope>CCPQU</scope><scope>D1I</scope><scope>DWQXO</scope><scope>HCIFZ</scope><scope>KB.</scope><scope>PDBOC</scope><scope>PQEST</scope><scope>PQQKQ</scope><scope>PQUKI</scope><orcidid>https://orcid.org/0000-0003-3064-1522</orcidid></search><sort><creationdate>20220801</creationdate><title>Junctionless Gate-all-around Nanowire FET with Asymmetric Spacer for Continued Scaling</title><author>Sreenivasulu, V. Bharath ; Narendar, Vadthiya</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c363t-faf37e8e152c8ad16eec045832958036217c4556b304023a659b2d2d3e787c723</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2022</creationdate><topic>Asymmetry</topic><topic>Chemistry</topic><topic>Chemistry and Materials Science</topic><topic>Dielectrics</topic><topic>Electrical properties</topic><topic>Environmental Chemistry</topic><topic>Hafnium oxide</topic><topic>Inorganic Chemistry</topic><topic>Lasers</topic><topic>Materials Science</topic><topic>Nanowires</topic><topic>Optical Devices</topic><topic>Optics</topic><topic>Original Paper</topic><topic>Photonics</topic><topic>Polymer Sciences</topic><topic>Power consumption</topic><topic>Power management</topic><topic>Scaling</topic><topic>Silicon dioxide</topic><topic>Silicon nitride</topic><topic>Transconductance</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Sreenivasulu, V. Bharath</creatorcontrib><creatorcontrib>Narendar, Vadthiya</creatorcontrib><collection>CrossRef</collection><collection>ProQuest SciTech Collection</collection><collection>ProQuest Technology Collection</collection><collection>Materials Science & Engineering Collection</collection><collection>ProQuest Central</collection><collection>AUTh Library subscriptions: ProQuest Central</collection><collection>Technology Collection</collection><collection>ProQuest One Community College</collection><collection>ProQuest Materials Science Collection</collection><collection>ProQuest Central</collection><collection>SciTech Premium Collection</collection><collection>Materials Science Database</collection><collection>Materials Science Collection</collection><collection>ProQuest One Academic Eastern Edition (DO NOT USE)</collection><collection>ProQuest One Academic</collection><collection>ProQuest One Academic UKI Edition</collection><jtitle>SILICON</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Sreenivasulu, V. Bharath</au><au>Narendar, Vadthiya</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Junctionless Gate-all-around Nanowire FET with Asymmetric Spacer for Continued Scaling</atitle><jtitle>SILICON</jtitle><stitle>Silicon</stitle><date>2022-08-01</date><risdate>2022</risdate><volume>14</volume><issue>13</issue><spage>7461</spage><epage>7471</epage><pages>7461-7471</pages><issn>1876-990X</issn><eissn>1876-9918</eissn><abstract>In this paper, we have performed the scaling of asymmetric junctionless (JL) SOI nanowire (NW) FET at 10 nm gate length (
L
G
). To study the device electrical performance various DC metrics like SS, DIBL,
I
ON
/
I
OFF
ratio are discussed. Even at 5 nm, the device has good electrical properties with subthreshold swing (SS) = ~64 mV/dec, drain induced barrier lowering (DIBL) = ~45 mV/V, and switching ratio (
I
ON
/
I
OFF
) = ~10
6
shows a higher level of electrostatic integrity. At 5 nm
L
G
with optimized spacer dielectric the device exhibits ~5 orders of improvement in
I
OFF
and the improvement is less than ~2 orders at 20 nm
L
G
. Thus, from the result analysis, the spacer dielectrics are essential at lower
L
G
for better performance. For continued scaling, the HfO
2
spacer dielectric ensures high performance with the lowest downfall in
I
ON
with 11.24% and the decline is 15.8% and 13.26% with no spacer and Si
3
N
4
respectively. With SiO
2
, Si
3
N
4
, and HfO
2
spacers the asymmetric spacer ensures an
I
ON
/
I
OFF
of ~10
6
which is permissible for ITRS low power requirements. Moreover, to study scaling flexibility towards analog/RF applications various parameters like transconductance (
g
m
), transconductance generation factor (TGF), total gate capacitance (
C
gg
), and cutoff frequency (
f
T
) are also determined. Furthermore, the scaling impact on dynamic power (DP) and static power (SP) consumption are also presented. The findings of the study show that asymmetric JL NW FET is one of the potential candidates for future technology nodes.</abstract><cop>Dordrecht</cop><pub>Springer Netherlands</pub><doi>10.1007/s12633-021-01471-z</doi><tpages>11</tpages><orcidid>https://orcid.org/0000-0003-3064-1522</orcidid><oa>free_for_read</oa></addata></record> |
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source | Springer Nature |
subjects | Asymmetry Chemistry Chemistry and Materials Science Dielectrics Electrical properties Environmental Chemistry Hafnium oxide Inorganic Chemistry Lasers Materials Science Nanowires Optical Devices Optics Original Paper Photonics Polymer Sciences Power consumption Power management Scaling Silicon dioxide Silicon nitride Transconductance |
title | Junctionless Gate-all-around Nanowire FET with Asymmetric Spacer for Continued Scaling |
url | http://sfxeu10.hosted.exlibrisgroup.com/loughborough?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-24T14%3A12%3A22IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_cross&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=Junctionless%20Gate-all-around%20Nanowire%20FET%20with%20Asymmetric%20Spacer%20for%20Continued%20Scaling&rft.jtitle=SILICON&rft.au=Sreenivasulu,%20V.%20Bharath&rft.date=2022-08-01&rft.volume=14&rft.issue=13&rft.spage=7461&rft.epage=7471&rft.pages=7461-7471&rft.issn=1876-990X&rft.eissn=1876-9918&rft_id=info:doi/10.1007/s12633-021-01471-z&rft_dat=%3Cproquest_cross%3E2919455240%3C/proquest_cross%3E%3Cgrp_id%3Ecdi_FETCH-LOGICAL-c363t-faf37e8e152c8ad16eec045832958036217c4556b304023a659b2d2d3e787c723%3C/grp_id%3E%3Coa%3E%3C/oa%3E%3Curl%3E%3C/url%3E&rft_id=info:oai/&rft_pqid=2919455240&rft_id=info:pmid/&rfr_iscdi=true |