Introduction of Metal Layer in Junctionless Accumulation Mode FET:-Proposal and Analysis

• Published in: SILICON 2022-11, Vol.14 (17), p.11619-11632
• Main Authors: Raushan, Mohd. Adil, Bashir, MD Yasir, Nishad, Shrikant, Ahmad, Shameem, Siddiqui, Mohammad Jawaid
• Format: Article
• Language: English
• Subjects: Accumulation; Business metrics; Chemical vapor deposition; Chemistry; Chemistry and Materials Science; Circuits; Electric fields; Environmental Chemistry; Inorganic Chemistry; Lasers; Materials Science; Misalignment; Optical Devices; Optics; Original Paper; Performance measurement; Photonics; Polymer Sciences; Simulation; Transconductance; Transistors; Work functions
• ISSN: 1876-990X; 1876-9918
• DOI: 10.1007/s12633-022-01879-1

In this paper, we have proposed single gate junctionless accumulation mode FET (JAM) and underlapped junctionless accumulation mode FET (UL-JAM) with metal layer implant in gate oxide at channel-drain interface (MI-JAM and UL-MI-JAM). This architectural addition of low work function metal layer in JAMFET reduces gate induced drain leakage (GIDL) considerably. It reduces the electric field assisting tunneling at channel-drain interface. Therefore, it improves overall ON-state to OFF-state current ratio by 2 orders for channel length 40 nm. I ON /I OFF is further improved by two orders in UL-JAM compared to MI-JAM. We also showed effect of metal layer misalignment at drain-channel interface and effect of inserted metal layer work function on various performance metrics such as early voltage, transconductance to current ratio etc. We have found considerable improvement in these metrics for UL-MI-JAM (2x) as compared to conventional JAM. Furthermore, we investigated the reliability of metal layer inserted devices with respect to temperature and trapped interface charges. Finally, to see the circuit performance of the devices we simulated a CMOS inverter using both conventional and proposed devices and compared different circuit performance matrices.