High-Speed Serial Optical Link Test Bench Using FPGA with Embedded Transceivers

• Published in: arXiv.org 2024-01
• Main Authors: Xiang, Annie C, Cao, Tingting, Gong, Datao, Hou, Suen, Liu, Chonghan, Liu, Tiankuan, Da-Shung, Su, Ping-Kun Teng, Ye, Jingbo
• Format: Article
• Language: English
• Subjects: Bit error rate; Error analysis; Sensitivity; Signal integrity
• ISSN: 2331-8422
• DOI: 10.48550/arxiv.2401.15754

We develop a custom Bit Error Rate test bench based on Altera's Stratix II GX transceiver signal integrity development kit, demonstrate it on point-to-point serial optical link with data rate up to 5 Gbps, and compare it with commercial stand alone tester. The 8B/10B protocol is implemented and its effects studied. A variable optical attenuator is inserted in the fibre loop to induce transmission degradation and to measure receiver sensitivity. We report comparable receiver sensitivity results using the FPGA based tester and commercial tester. The results of the FPGA also shows that there are more one-to-zero bit flips than zero-to-one bit flips at lower error rate. In 8B/10B coded transmission, there are more word errors than bit flips, and the total error rate is less than two times that of non-coded transmission. Total error rate measured complies with simulation results, according to the protocol setup.