Negative Capacitance Junctionless FinFET for Low Power Applications: An Innovative Approach

Recently, increasing power leakage has become a major concern especially in MOSFET based nanoscale devices due to poor gate control. To mitigate these problems, the devices with steep slope, low leakage and power consumption are required. In this context, this work introduced a novel concept of Nega...

Full description

Saved in:
Bibliographic Details
Published in:SILICON 2022-08, Vol.14 (12), p.6719-6728
Main Authors: Kaushal, Shelja, Rana, Ashwani K.
Format: Article
Language:English
Subjects:
Capacitance
Chemistry
Chemistry and Materials Science
Design
Design optimization
Electric fields
Environmental Chemistry
Ferroelectric materials
Ferroelectricity
Inorganic Chemistry
Lasers
Leakage current
Materials Science
Nanotechnology devices
Optical Devices
Optics
Original Paper
Performance enhancement
Photonics
Polymer Sciences
Power consumption
Power management
Simulation
Citations: Items that this one cites
Items that cite this one
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:Recently, increasing power leakage has become a major concern especially in MOSFET based nanoscale devices due to poor gate control. To mitigate these problems, the devices with steep slope, low leakage and power consumption are required. In this context, this work introduced a novel concept of Negative Capacitance (NC) effect with Junctionless Multi Gate FET to investigate various device performance parameters for nanoscale dimensions. The baseline approach of combining LK-equation with Sentaurus TCAD tool, was used to design and optimize a 14nm n-type Negative Capacitance Junctionless FinFET (NC-JL FinFET) with doped HfO 2 as gate ferroelectric material for low power applications. The impact of ferroelectric thickness, spacer and gate dielectric was analyzed using extensive device simulations. The results showed that the designed NC-JL FinFET exhibits enhanced performance with steep SS, Negative DIBL, lower leakage current and also higher drive current performance than JL FinFET. Further, the application of strain-engineering in NC-JL FinFET shows 12 % improvement in I ON /I OFF as compared to unstrained NC-JL FinFET.
ISSN:1876-990X
1876-9918
DOI:10.1007/s12633-021-01392-x