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Effect of Positive/Negative Interface Trap Charges on the Performance of Multi Fin FinFET (M-FinFET)

Multiple Fins structured FinFET (M-FinFET) is a promising semiconductor device for future improvisation of CMOS technology. In this paper, we investigate the impact of interface trap charges (positive and negative trap) at the HfO2/Si interface in M-FinFET for the first time. The various important D...

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Bibliographic Details
Published in:SILICON 2022-09, Vol.14 (14), p.8557-8566
Main Authors: Das, Rinku Rani, Maity, Santanu, Chowdhury, Atanu, Chakraborty, Apurba, Mitra, Suman Kumar
Format: Article
Language:English
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Summary:Multiple Fins structured FinFET (M-FinFET) is a promising semiconductor device for future improvisation of CMOS technology. In this paper, we investigate the impact of interface trap charges (positive and negative trap) at the HfO2/Si interface in M-FinFET for the first time. The various important DC attributes, RF/analog, and linearity metrics are studied in presence and absence of traps. Simultaneously, the various trap concentration effect on the characteristics of M-FinFET are also observed. The results show that the introduction of interface trap charges (ITC) has optimized the ON current, OFF current, and also improves sub-threshold swing (SS) characteristics as compared to no trap condition. It is observed that negative trap having trap concentration of 10 13 /cm 2 enhances the I ON by 1.64%, SS by 5.66%, and various important RF/analog parameter such as transconductance frequency product (GFP) improves by 1.25%, device efficiency by 37.12% and intrinsic gain (A v ) 90.38%. On the other hand, linearity parameters like VIP2, VIP3 and 1 dB compression point shows better performance in presence of positive and negative trap.
ISSN:1876-990X
1876-9918
DOI:10.1007/s12633-022-01669-9