Loading…
Investigation of CNTFET Based Energy Efficient Fast SRAM Cells for Edge AI Devices
A novel reduced power with enhanced speed (RPES) technique for Static Random Access Memory (SRAM) topologies using Carbon Nano Tube Field Effect Transistors (CNTFETs) instead of traditional MOSFETs which is in demand for edge AI devices, energy efficient deep neural networks, smart wearable devices...
Saved in:
Published in: | SILICON 2022-09, Vol.14 (14), p.8815-8830 |
---|---|
Main Authors: | , |
Format: | Article |
Language: | English |
Subjects: | |
Citations: | Items that this one cites Items that cite this one |
Online Access: | Get full text |
Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Summary: | A novel reduced power with enhanced speed (RPES) technique for Static Random Access Memory (SRAM) topologies using Carbon Nano Tube Field Effect Transistors (CNTFETs) instead of traditional MOSFETs which is in demand for edge AI devices, energy efficient deep neural networks, smart wearable devices and high-speed era is proposed in this paper. This work reduces propagation delay and sub-threshold leakage current using RPES technique with a power supply of 0.9V. The performance and power delay product (PDP) of 6T, 8T and 10T SRAM cells is analysed for CNTFET based RPES technique at 45nm technology. Simulated results using Stanford CNTFET model shows improvement in PDP of proposed 6T SRAM cell by 66% compared to Conv6T and 27% compared to Ternary 4TSTI 6T SRAM. Conv 8T and Diff 8T are implemented using RPES technique which shows improvement by 40.9% and 74.3% respectively. Among SE10T and Diff 10T topologies, Diff 10T has better PDP when implemented using RPES technique. All SRAM cells mentioned are analyzed for various high-k dielectric materials, oxide thickness and pitch values of CNTFET and best fitting results are proposed for SRAM cells. |
---|---|
ISSN: | 1876-990X 1876-9918 |
DOI: | 10.1007/s12633-021-01589-0 |