Analysis of Degradation Mechanism in Poly-Si TFTs under Dynamic Gate Voltage Stress with Short Pulse Width Duration

Degradation behaviors of polycrystalline silicon thin-film transistors under dynamic gate voltage stress with short pulse width duration are systematically investigated for the first time. Both the peak voltage duration and the base voltage duration have an impact on the hot carrier degradation of t...

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Bibliographic Details
Published in:IEEE electron device letters 2024-02, Vol.45 (2), p.1-1
Main Authors: Zhang, Meng, Jiang, Zhendong, Lu, Lei, Wong, Man, Kwok, Hoi-Sing
Format: Article
Language:English
Subjects:
Degradation
Electric potential
emission time
Junctions
Logic gates
Nonequilibrium junction degradation model
polycrystalline silicon
Polysilicon
Pulse duration
recapture time
Reliability
Semiconductor devices
Short pulses
Silicon films
Stress
Thin film transistors
Voltage
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Summary:Degradation behaviors of polycrystalline silicon thin-film transistors under dynamic gate voltage stress with short pulse width duration are systematically investigated for the first time. Both the peak voltage duration and the base voltage duration have an impact on the hot carrier degradation of the device. Incorporated with simulations, an advanced model for nonequilibrium junction degradation is proposed.
ISSN:0741-3106
1558-0563
DOI:10.1109/LED.2023.3345282