L Style n-MOSFET Layout For Mitigating TID Effects

This paper proposes a new rad hard layout L style of nmos metal oxide semiconductor field effect transistor (n-MOSFET), which is evaluated to show that its efficacy at reducing radiation-induced leakage currents, thus improving the total ionization dose(TID) tolerance with very less area and parasit...

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Bibliographic Details
Published in:SILICON 2022-06, Vol.14 (8), p.3891-3898
Main Authors: Malik, Munish, Prakash, Neelam R., Kumar, Ajay, Jatana, H.S.
Format: Article
Language:English
Subjects:
Chemistry
Chemistry and Materials Science
Circuits
CMOS
Cosmic rays
Electrons
Environmental Chemistry
Field effect transistors
Inorganic Chemistry
Lasers
Layouts
Leakage current
Materials Science
Metal oxide semiconductors
Metal oxides
MOSFETs
Nuclear energy
Nuclear power plants
Optical Devices
Optics
Original Paper
Parasitics (electronics)
Photonics
Polymer Sciences
Radiation
Radiation effects
Semiconductor devices
Silicon
Transistors
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Summary:This paper proposes a new rad hard layout L style of nmos metal oxide semiconductor field effect transistor (n-MOSFET), which is evaluated to show that its efficacy at reducing radiation-induced leakage currents, thus improving the total ionization dose(TID) tolerance with very less area and parasitic capacitance as compared to enclosed layout transistor(ELT). This proposed layout structure is fully compatible to present commercial fabrication technology without any additional mask requirement as compared to conventional n MOSFET fabrication and can be used as radiation tolerant by design technique. The simulated I D - V G characteristics of the rad hard L n-MOSFET layout demonstrated the effectiveness of eliminating radiation-induced leakage current paths. The leakage current in proposed rad hard L n-MOSFET has been reduced by factor of 10 8 at 300Krad dose as compared to conventional layout n-MOSFET.
ISSN:1876-990X
1876-9918
DOI:10.1007/s12633-021-01150-z