Radiation-Immune Spintronic Binary Synapse and Neuron for Process-in-Memory Architecture

This letter proposes a single event upset (SEU)-hardened task-scheduling logic-in-memory xnor/xor neuron and synapse circuit. Using a C-element and a magnetic tunnel junction enhances immunity against SEU injection. Also, using logic-in-memory architecture eliminates the need to access external memo...

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Bibliographic Details
Published in:IEEE magnetics letters 2024, Vol.15, p.1-5
Main Authors: Nasab, Milad Tanavardi, Amirany, Abdolah, Moaiyeri, Mohammad Hossein, Jafari, Kian
Format: Article
Language:English
Subjects:
<sc xmlns:ali="http://www.niso.org/schemas/ali/1.0/" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">xnor neuron
carbon nanotube field-effect transistor
Carbon nanotubes
CNTFETs
Delay
Field effect transistors
Hardware
In-memory computing
magnetic tunnel junction
Magnetic tunneling
Memory architecture
Neurons
Resistance
Semiconductor devices
single event upset-hardened
Single event upsets
Spin electronics
Spintronics
Task scheduling
Tunnel junctions
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Summary:This letter proposes a single event upset (SEU)-hardened task-scheduling logic-in-memory xnor/xor neuron and synapse circuit. Using a C-element and a magnetic tunnel junction enhances immunity against SEU injection. Also, using logic-in-memory architecture eliminates the need to access external memory and decreases power and delay. Furthermore, using a carbon nanotube field-effect transistor leads to lower leakage and static current caused by higher gate control in these transistors. Compared to the state-of-the-art counterparts, the developed design offers at least 31%, 17%, and 3% improvement in power, power delay product, and power delay area product, respectively.
ISSN:1949-307X
1949-3088
DOI:10.1109/LMAG.2024.3356815