A 0.079-pJ/b/dB 32-Gb/s 2× Half-Baud-Rate CDR Circuit With Frequency Detector

A 32-Gb/s [Formula Omitted] half-baud-rate (THBR) clock and data recovery (CDR) circuit is presented by using a phase detector (PD) and a frequency detector (FD). The frequency detection range of the FD is analyzed. This prototype is fabricated in a 28-nm CMOS process with an active area of 0.055 mm...

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Bibliographic Details
Published in:IEEE transactions on very large scale integration (VLSI) systems 2024-04, Vol.32 (4), p.704-713
Main Authors: Lan, Yi-Hao, Liu, Shen-Iuan
Format: Article
Language:English
Subjects:
Bit error rate
CDR circuits
Clock recovery
Data recovery
Figure of merit
Phase detectors
Power consumption
Pseudorandom
Pseudorandom sequences
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Summary:A 32-Gb/s [Formula Omitted] half-baud-rate (THBR) clock and data recovery (CDR) circuit is presented by using a phase detector (PD) and a frequency detector (FD). The frequency detection range of the FD is analyzed. This prototype is fabricated in a 28-nm CMOS process with an active area of 0.055 mm2. The measured frequency capture range is 43.7% for a 32-Gb/s pseudorandom bit sequence (PRBS) of 27-1. This proposed CDR circuit achieves a bit error rate of less than [Formula Omitted] under the channel loss of 23 dB at 16 GHz. The total power consumption is 58.6 mW at 32 Gb/s and achieves a figure-of-merit (FoM) of 0.079 pJ/bit/dB.
ISSN:1063-8210
1557-9999
DOI:10.1109/TVLSI.2023.3330012