High-Pressure Deuterium Annealing for Trap Passivation for a 3-D Integrated Structure

• Published in: IEEE transactions on electron devices 2024-04, Vol.71 (4), p.1-4
• Main Authors: Lee, Jung-Woo, Han, Joon-Kyu, Wang, Dong-Hyun, Yun, Seong-Yun, Oh, Jeong-Seob, Bang, Byeong-Chan, Cha, Won-Hyo, Park, Jun-Young, Choi, Yang-Kyu
• Format: Article
• Language: English
• Subjects: 3-D architecture; Annealing; border trap density (<inline-formula xmlns:ali="http://www.niso.org/schemas/ali/1.0/" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"> <tex-math notation="LaTeX"> textit{N}_{{\text{bt}}}\text{)}</tex-math> </inline-formula>; Current voltage characteristics; Density; Deuterium; forming gas annealing (FGA); High pressure; high-pressure deuterium annealing (HPDA); interface trap density (<inline-formula xmlns:ali="http://www.niso.org/schemas/ali/1.0/" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"> <tex-math notation="LaTeX"> textit{N}_{{\text{it}}}\text{)}</tex-math> </inline-formula>; LF noise; low-frequency noise (LFN); monolithic integration; MOSFETs; on-state current (<inline-formula xmlns:ali="http://www.niso.org/schemas/ali/1.0/" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"> <tex-math notation="LaTeX"> textit{I}_{{\text{ON}}}\text{)}</tex-math> </inline-formula>; passivation; Performance indices; Polysilicon; Semiconductor devices; Silicon; subthreshold swing (SS); Thin film transistors
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/TED.2024.3371422

High-pressure deuterium annealing (HPDA) and forming gas annealing (FGA) were applied to monolithically and vertically integrated MOSFETs with a 3-D architecture of one over the other. An overlying poly-Si thin-film transistor (TFT) is positioned over an underlying MOSFET onto a wafer of silicon-on-insulator (SOI). The effects of HPDA and FGA on these double-stacked MOSFETs were quantitatively analyzed by extracting the interface trap density ( {\textit{N}}_{{\text{it}}} ) from dc I-V characteristics and border trap density ( {\textit{N}}_{{\text{bt}}} ) through low-frequency noise (LFN) measurements. The performance index parameters, such as subthreshold swing (SS) and on-state current ( \textit{I}_{{\text{ON}}} ), were also comparatively analyzed. It has been confirmed that, for the superjacent MOSFET, HPDA reduced \textit{N}_{{\text{it}}} by 250% and \textit{N}_{{\text{bt}}} by 92% compared to FGA. Additionally, for the subjacent MOSFET, HPDA decreased \textit{N}_{{\text{it}}} by 15% and \textit{N}_{{\text{bt}}} by 32% compared to FGA.