A New High Density 3D Stackable Via RRAM for Computing-in-Memory SOC Applications

A novel 3D stackable Via resistive random access memory (RRAM) latch and Via RRAM logic gates implemented in 16-nm FinFET logic process for computing-in-memory (CIM) applications are proposed. Via RRAM latch array can provide more than 60 Mb/mm2 of latch storage density to achieve stable full-swing...

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Bibliographic Details
Published in:IEEE transactions on electron devices 2024-04, Vol.71 (4), p.1-5
Main Authors: Sing, Siao-Ping, Wang, Ya-Ching, Lin, Wei-Hwa, Chih, Yue-Der, Wang, Yih, King, Ya-Chin, Lin, Chrong Jung
Format: Article
Language:English
Subjects:
Arrays
Artificial synapse
CMOS logic
Common Information Model (computing)
Computation
computing-in-memory (CIM)
Density
Gates (circuits)
Latches
Layout
Logic circuits
Logic gates
multiply–accumulate (MAC)
neural network (NN)
Random access memory
Resistance
resistive random access memory (RRAM)
Three-dimensional displays
Voltage
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Summary:A novel 3D stackable Via resistive random access memory (RRAM) latch and Via RRAM logic gates implemented in 16-nm FinFET logic process for computing-in-memory (CIM) applications are proposed. Via RRAM latch array can provide more than 60 Mb/mm2 of latch storage density to achieve stable full-swing high-speed output. By simplifying the readout circuit, latch array allows flexible configuration in advanced SOC. Three-Dimensional Via RRAM logic gates compute the stored data internally. The features show a promising way to reduce the von Neumann bottleneck.
ISSN:0018-9383
1557-9646
DOI:10.1109/TED.2024.3367661