Ka-Band Three-Stacked CMOS Power Amplifier With LC Shunt-Feedback to Enhance Gain and Stability

In this study, we designed a Ka-band three-stacked CMOS power amplifier (PA) to obtain high output power. Due to the positive feedback path attributed to the complexity of the three-stacked power stage layout, typical capacitive neutralization techniques alone are insufficient to achieve high gain a...

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Bibliographic Details
Published in:IEEE transactions on circuits and systems. II, Express briefs Express briefs, 2024-04, Vol.71 (4), p.1-1
Main Authors: Kim, Taehun, Park, Changkun
Format: Article
Language:English
Subjects:
Amplification
Circuit stability
CMOS
Extremely high frequencies
Gain
High gain
Inductance
Layout
Logic gates
millimeter-wave
neutralization technique
Parasitics (electronics)
Performance degradation
Positive feedback
power amplifier
Power amplifiers
Power generation
Power semiconductor devices
Quadrature amplitude modulation
Simulation
Stability
stack structure
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Summary:In this study, we designed a Ka-band three-stacked CMOS power amplifier (PA) to obtain high output power. Due to the positive feedback path attributed to the complexity of the three-stacked power stage layout, typical capacitive neutralization techniques alone are insufficient to achieve high gain and stability at the same time. To solve this problem, we proposed an LC shunt-feedback technique that can alleviate performance degradation caused by parasitic inductance in the gate node of a power transistor. We designed a PA using a 65-nm RFCMOS process to verify the utility of the proposed structure. At 38 GHz, the proposed PA achieves output 1-dB compression point (OP1dB) of 18.8 dBm, saturation output power (PSAT) of 22.0 dBm, peak power-added efficiency (PAE) of 21.9%, and small signal gain of 32.2 dB, respectively. The PA is measured with 64-quadrature amplitude modulation (QAM) signals, which has a 100-MHz channel bandwidth and a 9.7-dB peak-to-average power ratio (PAPR). At 38GHz, the PA achieves output power of 13.8-dBm with -25-dB error vector magnitude (EVM) and the adjacent channel leakage ratio (ACLR) of -28.1 dBc, respectively. The chip and core sizes of the power amplifier are 0.342 mm2 and 0.096 mm2, respectively.
ISSN:1549-7747
1558-3791
DOI:10.1109/TCSII.2023.3332874