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A Method for Deembedding the Mounting Pad and Via-Hole Effect in a Test Fixture for Accurate Impedance Measurement of the Surface Mount Device Component
In this article, we propose a method for deembedding the effects of mounting pads and via-holes in test fixture for accurate impedance measurement of the passive component of surface mount devices (SMDs). Impedance of the SMD passive component is measured mounted on the test fixture because it canno...
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Published in: | IEEE transactions on instrumentation and measurement 2024, Vol.73, p.1-13 |
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Main Authors: | , , , , , , |
Format: | Article |
Language: | English |
Subjects: | |
Citations: | Items that this one cites |
Online Access: | Get full text |
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Summary: | In this article, we propose a method for deembedding the effects of mounting pads and via-holes in test fixture for accurate impedance measurement of the passive component of surface mount devices (SMDs). Impedance of the SMD passive component is measured mounted on the test fixture because it cannot be probed directly. Hence, the measurement results include the effects of the test fixture. Deembedding is required to extract the impedance of the device under test alone. Existing deembedding methods such as short-open-load-thru (SOLT), thru-reflect-line (TRL), and 2x thru deembedding cannot eliminate the effects of the mounting pads and via-holes of the test fixture, leading to large measurement errors. Our proposed method can extract the parasitic components of the mounting pads and via-hole using open and short fixtures, and then deembed the mounting pads and via-hole. Furthermore, two guidelines for designing the short and open fixtures are proposed. We validated our proposed method through a simulation and measurement. From the measurement result of the multilayer ceramic capacitors, the difference in the equivalent series inductance (ESL) between the 2x thru deembedding method and the proposed method was analyzed. Additionally, we confirmed that the self-impedance and SSN voltage of the power distribution network (PDN) had larger value due to the ESL error. By reducing the ESL error, the SSN voltage was decreased by about 5%, thus saving the number of decoupling capacitors. |
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ISSN: | 0018-9456 1557-9662 |
DOI: | 10.1109/TIM.2024.3394503 |