Design and verification of an FPGA programmable logic element based on Sense-Switch pFLASH

This paper proposes a kind of programmable logic element (PLE) based on Sense-Switch pFLASH technology. By programming Sense-Switch pFLASH, all three-bit look-up table (LUT3) functions, partial four-bit look-up table (LUT4) functions, latch functions, and d flip flop (DFF) with enable and reset func...

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Bibliographic Details
Published in:Frontiers of information technology & electronic engineering 2024-03, Vol.25 (4), p.485-499
Main Authors: Cao, Zhengzhou, Liu, Guozhu, Zhang, Yanfei, Shan, Yueer, Xu, Yuting
Format: Article
Language:English
Subjects:
Application specific integrated circuits
Boolean
Combinatorial analysis
Communications Engineering
Computer Hardware
Computer Science
Computer Systems Organization and Communication Networks
Design
Digital signal processors
Electrical Engineering
Electronics and Microelectronics
Field programmable gate arrays
Instrumentation
Integrated circuits
Leakage current
Logic circuits
Lookup tables
Networks
Performance evaluation
Radiation
Random access memory
Research Article
Transistors
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Summary:This paper proposes a kind of programmable logic element (PLE) based on Sense-Switch pFLASH technology. By programming Sense-Switch pFLASH, all three-bit look-up table (LUT3) functions, partial four-bit look-up table (LUT4) functions, latch functions, and d flip flop (DFF) with enable and reset functions can be realized. Because PLE uses a choice of operational logic (COOL) approach for the operation of logic functions, it allows any logic circuit to be implemented at any ratio of combinatorial logic to register. This intrinsic property makes it close to the basic application specific integrated circuit (ASIC) cell in terms of fine granularity, thus allowing ASIC-like cell-based mappers to apply all their optimization potential. By measuring Sense-Switch pFLASH and PLE circuits, the results show that the “on” state driving current of the Sense-Switch pFLASH is about 245.52 µA, and that the “off” state leakage current is about 0.1 pA. The programmable function of PLE works normally. The delay of the typical combinatorial logic operation AND3 is 0.69 ns, and the delay of the sequential logic operation DFF is 0.65 ns, both of which meet the requirements of the design technical index.
ISSN:2095-9184
2095-9230
DOI:10.1631/FITEE.2300454