Wide Area Measurement-Based Cyber-Attack-Resilient Breaker Failure Protection Scheme

Breaker Failure Protection trips the backup breakers when the primary breaker fails, causing a significant loss of load. Hence, a cyber-attack on the Breaker Failure Protection scheme may lead to major disturbance in a power system. Currently, there is a lack of literature addressing the cyber-attac...

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Bibliographic Details
Published in:IEEE transactions on smart grid 2024-07, Vol.15 (4), p.4228-4244
Main Authors: Dubal, Paawan Kirankumar, Das, Sarasij, Sidhu, Tarlochan S.
Format: Article
Language:English
Subjects:
Algorithms
breaker failure protection
Circuit breakers
Circuit faults
Cyber-attack
Cyberattack
Cybersecurity
Digital relays
Failure
IEEE Standards
Measuring instruments
Phasor measurement units
Phasors
power system protection
Relay
Substations
synchrophasors
wide area measurements
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Summary:Breaker Failure Protection trips the backup breakers when the primary breaker fails, causing a significant loss of load. Hence, a cyber-attack on the Breaker Failure Protection scheme may lead to major disturbance in a power system. Currently, there is a lack of literature addressing the cyber-attack on Breaker Failure Protection scheme. This paper proposes a novel Wide Area Measurement-based cyber-attack-resilient Breaker Failure Protection scheme. Modern digital relays have Phasor Measurement Unit (PMU) integrated with them. A digital relay with PMU functionality is called Relay-PMU in this work. The proposed scheme has two parts. Part 1 is named as Synchrophasor-based Fault Validation Algorithm. It checks whether the Breaker Failure Protection operation is genuine or due to a cyber-attack. Breaker Failure Protection Relay-PMU will trigger the Part 1 of the proposed scheme which runs in a Phasor Data Concentrator. A novel concept named Dynamic Relay White-listing is proposed to avoid the usage of phasors from the susceptible Relay-PMUs. Part 2 is the modifications to the logics of the existing common Breaker Failure Protection schemes to incorporate the decision from the Synchrophasor-based Fault Validation Algorithm. The proposed scheme is computationally efficient and compatible with all common Breaker Failure Protection schemes. PSCAD simulations of the IEEE-118 bus system validate the proposed scheme. The execution time of the proposed scheme in the lab implementation setup adheres to the timeline of the Breaker Failure Protection scheme.
ISSN:1949-3053
1949-3061
DOI:10.1109/TSG.2024.3372632