A 0.055 mm2 Total Area Triple-Loop Wideband Fractional-N All-Digital Phase-Locked Loop Architecture for 1.9–6.1 GHz Frequency Tuning

• Published in: Electronics (Basel) 2024-07, Vol.13 (13), p.2638
• Main Authors: Kang, Byeongseok, Kim, Youngsik, Son, Hyunwoo, Kim, Shinwoong
• Format: Article
• Language: English
• Subjects: Automatic control; Automatic frequency control; Broadband; Calibration; Design; Frequency control; Frequency dividers; Frequency ranges; Internet of Things; Locking; Phase locked loops; Power consumption; Search engines; Tuning
• ISSN: 2079-9292; 2079-9292
• DOI: 10.3390/electronics13132638

This paper presents a wideband fractional-N all-digital phase-locked loop (WBPLL) architecture featuring a triple-loop configuration capable of tuning frequencies from 1.9 to 6.1 GHz. The first and second loops, automatic frequency control (AFC) and counter-assisted phase-locked loop (CAPLL), respectively, perform coarse locking, while the third loop employs a digital sub-sampling architecture without a frequency divider for fine locking. In this third loop, fractional-N frequency synthesis is achieved using a delta-sigma modulator (DSM) and digital-to-time converter (DTC). To minimize area, digital modules such as counters, comparators, and differentiators used in the AFC and CAPLL loops are reused. Furthermore, a moving average filter (MAF) is employed to reduce the frequency overlap ratio of the digitally controlled oscillator (DCO) between the second and third loops, ensuring stable loop switching. The total power consumption of the WBPLL varies with the frequency range, consuming between 8.8 mW at the WBPLL minimum output frequency of 1.9 GHz and 12.8 mW at the WBPLL maximum output frequency of 6.1 GHz, all at a 1.0 V supply. Implemented in a 28 nm CMOS process, the WBPLL occupies an area of 0.055 mm2.