P‐52: Scalable Multi‐layered Real‐time Holography Processor Architecture with High Bandwidth Memory (HBM)

In this paper, we present a fast and efficiently scalable 3D holographic video processor using a layer‐based method using a modified inverse Fresnel transform. In our previous paper, we designed a single‐layer holographic core using a fixed‐point model and tested its operation on an FPGA. This paper...

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Bibliographic Details
Published in:SID International Symposium Digest of technical papers 2024-06, Vol.55 (1), p.1563-1566
Main Authors: Kwon, Wonok, Cheon, Sanghoon
Format: Article
Language:English
Subjects:
Computer‐generated hologram
Hologram
Holograms
Holography
Light modulators
Microprocessors
Multi‐layered hologram
Real‐time holography processor
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Summary:In this paper, we present a fast and efficiently scalable 3D holographic video processor using a layer‐based method using a modified inverse Fresnel transform. In our previous paper, we designed a single‐layer holographic core using a fixed‐point model and tested its operation on an FPGA. This paper implements an 8‐layer, 15FPS real‐time hologram processor by receiving RGB and depth input. For fast CGH processing, we utilized HBM memory, which is faster than DDR4, to store FFT results. After applying 2× linear interpolation, the implemented real‐time holography processor converts into real‐time holograms using a 4K color space light modulator
ISSN:0097-966X
2168-0159
DOI:10.1002/sdtp.17856