Low-jitter DLL applied for two-segment TDC

• Published in: IET circuits, devices & systems devices & systems, 2018-01, Vol.12 (1), p.17-24
• Main Authors: Wu, Jin, Zhang, Youzhi, Zhao, Rongqi, Zhang, Kunpeng, Zheng, Lixia, Sun, Weifeng
• Format: Article
• Language: English
• Subjects: charge pump; charge pump circuits; Charge pumps; clock jitter; clock period counting; Clocks; Clocks & watches; CMOS; CMOS integrated circuits; Control theory; current matching; Data transmission; Delay lines; delay lock loops; delay-locked loop; discharging currents; eight-phase discrimination; Feedback loops; frequency 60 MHz to 240 MHz; Frequency locking; high-resolution time-to-digital converter; interior feedback loop; Linearity; linearity property; locked state; low-jitter DLL; low-jitter outputs; mean square error methods; Noise reduction; noise suppression; phase detector; Phase detectors; Phase matching; Research Article; root mean square; Segments; size 0.35 mum; static phase offset; time 3.6 ps; time 35.07 ps; time-digital conversion; timing jitter; TSMC complementary metal–oxide–semiconductor process; two-segment TDC; uniformly distributed multiphase clocks; VCDL; Vibration; voltage-controlled delay line
• ISSN: 1751-858X; 1751-8598; 1751-8598
• DOI: 10.1049/iet-cds.2016.0342

A low-jitter delay-locked loop (DLL) for high-resolution time-to-digital converter (TDC) is proposed in this study. The generated high accurate and low-jitter outputs with uniformly distributed multiphase clocks directly from the voltage-controlled delay line (VCDL) in DLL are applied to two-segment TDC. For reducing the static phase offset in locked state, the charge pump with interior feedback loop is used to achieve a better current matching between the charging and discharging currents. An improved phase detector as well as a differential VCDL excellent in linearity property and noise suppression is utilised for reducing the output clock jitter. Fabricated by TSMC 0.35 μm complementary metal–oxide–semiconductor process, the measurement results show that DLL's frequency locking range is 60–240 MHz, the output clock jitters at 125 MHz are 3.6 ps for root mean square and 35.07 ps for peak-to-peak. By clock period counting and eight-phase discrimination, the resolution of