Fast signed multiplier using Vedic Nikhilam algorithm

Vedic algorithm is beneficial for the application in the design of high-speed computing and hardware. This study presents a fast signed binary multiplication structure based on Vedic Nikhilam algorithm. The authors explored the Nikhilam sutra for unsigned decimal numbers to both signed decimal and b...

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Bibliographic Details
Published in:IET circuits, devices & systems devices & systems, 2020-11, Vol.14 (8), p.1160-1166
Main Authors: Sahu, Satya Ranjan, Bhoi, Bandan Kumar, Pradhan, Manoranjan
Format: Article
Language:English
Subjects:
Algorithms
binary operands
combinational delay
digital arithmetic
fast signed binary multiplication structure
field programmable gate array devices
Field programmable gate arrays
high‐speed computing
logic design
Mathematics
Multiplication
multiplier architecture
Multipliers
multiplying circuits
Nikhilam sutra
Number systems
operand multiplication
Research Article
signed decimal
unsigned decimal numbers
Vedic Nikhilam algorithm
Xilinx ISE 14.4 software
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Summary:Vedic algorithm is beneficial for the application in the design of high-speed computing and hardware. This study presents a fast signed binary multiplication structure based on Vedic Nikhilam algorithm. The authors explored the Nikhilam sutra for unsigned decimal numbers to both signed decimal and binary operands. The proposed multiplier leads to significant gains in speed by converting a large operand multiplication to small operand multiplication, along with addition. The proposed design is synthesised with Xilinx ISE 14.4 software and realised using different field programmable gate array devices. The efficiency of the proposed design depends on combinational delay, area and power. Moreover, the new multiplier architecture achieves speed improvement over prior design.
ISSN:1751-858X
1751-8598
DOI:10.1049/iet-cds.2019.0537