Device-level XPS analysis for physical and electrical characterization of oxide-channel thin-film transistors

• Published in: Journal of applied physics 2024-08, Vol.136 (7)
• Main Authors: Cho, Yun-Ju, Kwon, Young-Ha, Seong, Nak-Jin, Choi, Kyu-Jeong, Lee, Myung Keun, Kim, Gyungtae, Yoon, Sung-Min
• Format: Article
• Language: English
• Subjects: Atomic properties; Bias; Composition effects; Effectiveness; Electrical properties; Indium gallium zinc oxide; Photoelectrons; Semiconductor devices; Thin film transistors; Transistors; X ray photoelectron spectroscopy
• ISSN: 0021-8979; 1089-7550
• DOI: 10.1063/5.0225676

This work aims to validate the feasibility of device-level analysis to reflect the effects of fabrication processes and operations, as contrasted with the conventional method of x-ray photoelectron spectroscopy (XPS), which is widely employed in amorphous oxide semiconductor thin-film transistors (TFTs) but analyzes film-level specimens. First, an analysis setup was introduced to determine the optimal x-ray target position for device-level XPS, where the intensity of channel components is maximized, through imaging XPS. Then, to demonstrate the effectiveness of this approach, the impact of channel composition and bias-stress was investigated through the implementation of device-level XPS on bottom-gate InGaZnO TFTs. The cationic composition ratios of the fabricated TFTs varied from 0.27:1:1.33 (In:Ga:Zn) and 0.28:1:2.21 when the subcycle of the Zn precursor increased by a factor of 1.5 in the atomic-layer deposition process. The device with a higher Zn ratio exhibited a more negative turn-on voltage and a twice larger subthreshold swing. These characteristics were validated from the comparisons in the relative amount of oxygen vacancies in O 1s of the channel and interface regions by 8.4%p and 5.6%p, respectively, between the devices. Furthermore, the electron trapping effect was verified for the devices subjected to a positive gate bias-stress of 3 MV/cm, as evidenced by the changes in the binding energy difference (0.35 eV) between the channel and gate insulator layers, in comparison to the non-stressed device. Consequently, this work demonstrates that device-level XPS can be an effective tool for understanding TFTs' characteristics in various ways beyond film-level analysis.