Novel Power-Efficient Fast-Locking Phase-Locked Loop Based on Adaptive Time-to-Digital Converter-Aided Acceleration Compensation Technology

This paper proposes an adaptive acceleration lock compensation technology for phase-locked loops (PLLs) based on a novel dual-mode programmable ring voltage-controlled oscillator (ring-VCO). In addition, a time-to-digital converter (TDC) is designed to accurately quantify the phase difference from t...

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Bibliographic Details
Published in:Electronics (Basel) 2024-09, Vol.13 (18), p.3586
Main Authors: Sun, Ligong, Luo, Yixin, Deng, Zhiyao, Wang, Jinchan, Liu, Bo
Format: Article
Language:English
Subjects:
Accuracy
Charge pumps
Communications systems
Compensation
Design
Design optimization
Design standards
Efficiency
Energy dissipation
Energy use
Locking
Multiple objective analysis
Phase locked loops
Phase noise
Power efficiency
Power electronics
Reference signals
Technology application
Technology assessment
Topology optimization
Tradeoffs
Voltage controlled oscillators
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Summary:This paper proposes an adaptive acceleration lock compensation technology for phase-locked loops (PLLs) based on a novel dual-mode programmable ring voltage-controlled oscillator (ring-VCO). In addition, a time-to-digital converter (TDC) is designed to accurately quantify the phase difference from the phase frequency detector (PFD) in order to optimize the dead-zone effect while dynamically switching an auxiliary charge pump (CP) module to realize fast phase locking. Furthermore, a TDC-controlled three/five-stage dual-mode adaptively continuously switched VCO is proposed to optimize the phase noise (PN) and power efficiency, leading to an optimal performance tradeoff of the PLL. Based on the 180 nm/1.8 V standard CMOS technology, the complete PLL design and a corresponding simulation analysis are implemented. The results show that, with a 1 GHz reference signal as the input, the output frequency is 50–324 MHz, with a wide tuning range of 260 MHz and a low phase noise of −98.07 dBc/Hz@1 MHz. The key phase-locking time is reduced to 1.11 μs, and the power dissipation is lowered to 1.86 mW with a layout area of 66 μm × 128 μm. A significantly remarkable multiobjective performance tradeoff with topology optimization is realized, which is in contrast to several similar design cases of PLLs.
ISSN:2079-9292
2079-9292
DOI:10.3390/electronics13183586