FPUx: High-Performance Floating-Point Support for Cost-Constrained RISC-V Cores

In the Internet of Things (IoT) field, cloud and fog computing dramatically increase the complexity of floating-point (FP) calculations. Cost-constrained microcontrollers (MCUs) urgently need more efficient FP computing methods, such as integrated FP units (FPUs). To this end, this brief proposes FP...

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Bibliographic Details
Published in:IEEE transactions on very large scale integration (VLSI) systems 2024-10, Vol.32 (10), p.1945-1949
Main Authors: Lin, Xian, Liu, Heming, Zheng, Xin, Gao, Huaien, Cai, Shuting, Xiong, Xiaoming
Format: Article
Language:English
Subjects:
Arithmetic
Constraints
Edge computing
Energy consumption
Floating point arithmetic
Floating-point units (FPUs)
Hardware
Internet of Things
Internet of Things (IoT)
IP networks
Pipelines
Pipelining (computers)
RISC
RISC-V
single-precision floating-point (FP) arithmetic IPs
State machines
Timing
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Summary:In the Internet of Things (IoT) field, cloud and fog computing dramatically increase the complexity of floating-point (FP) calculations. Cost-constrained microcontrollers (MCUs) urgently need more efficient FP computing methods, such as integrated FP units (FPUs). To this end, this brief proposes FPUx, a high-performance FPU designed through a hybrid pipeline and state-machine approach. The FPUx is integrated into E203 for implementation (E203-FPUx). Furthermore, the Easy-lite is proposed to reduce handshake delay and a range of single-precision FP (FP32) arithmetic IPs are designed to customize FPUs. Compared with E203-FPnew and E203, the performance of E203-FPUx is improved by 1.5\times and 36\times , and the total energy consumption is saved by 36% and 1430% on average, respectively.
ISSN:1063-8210
1557-9999
DOI:10.1109/TVLSI.2024.3399221