An 88 dB SNDR 100 kHz BW Sturdy MASH Delta-Sigma Modulator Using Self-Cascoded Floating Inverter Amplifiers

• Published in: Electronics (Basel) 2024-10, Vol.13 (19), p.3865
• Main Authors: Hao, Xirui, Yuan, Yidong, Pan, Jie, Lu, Zhaonan, Song, Shuang, Yu, Xiaopeng, Zhao, Menglian
• Format: Article
• Language: English
• Subjects: Amplifiers; Amplifiers (Electronics); Analog to digital converters; Bandwidths; Design; Figure of merit; High resolution; Internet of Things; Inverters; Modulators; Noise levels; Noise measurement; Technology application
• ISSN: 2079-9292; 2079-9292
• DOI: 10.3390/electronics13193865

Battery-powered Internet-of-Things applications require high-resolution, energy-efficient analog-to-digital converters (ADCs). There are still limited works on sub-MHz-bandwidth ADC designs. This paper presents a sturdy multi-stage shaping (SMASH) discrete-time (DT) delta-sigma modulator (DSM) structure using a self-cascoded floating-inverter-based dynamic amplifier (FIA). The proposed structure removes the explicit quantization error extraction of the first loop and all the feedback DACs in the cascaded loop, decreasing the design complexity of the circuit. This enables the proposed DT DSM to operate at a higher speed, which is suitable for achieving high-order noise at a low oversampling ratio (OSR). The proposed self-cascoded FIA is more power-efficient and can acquire more than 45 dB DC gain under a 1.2 V supply. The DT DSM implemented in a piece of 55 nm CMOS technology measures an 88.0 dB peak signal-to-noise-and-distortion ratio (SNDR) in a 100 kHz bandwidth (BW) and an 85.3 dB dynamic range (DR), consuming 249.1 μW from a 1.2 V supply at 10 MS/s. The obtained 174.0 dB SNDR-based Schreier figure-of-merit (FoMs) is competitive within state-of-art high-resolution (SNDR > 85 dB) and general-purpose (sub-MHz-bandwidth) ΔΣ ADCs.