Novel High-Speed State-of-Charge Alignment Algorithm for EV Battery Maintenance

• Published in: IEEE transactions on industrial electronics (1982) 2024-12, Vol.71 (12), p.15724-15733
• Main Authors: Nguyen, Nguyen-Anh, La, Phuong-Ha, Choi, Sung-Jin
• Format: Article
• Language: English
• Subjects: Algorithms; Alignment; Balancing; Batteries; Battery maintenance; battery swapping; Charge transfer; charge transfer strategy; Charging; charging and equalizing strategy; Deviation; Electric charge; Electric vehicles; Equalizers; full-duplex; Full-duplex system; Hardware; Maintenance; Maintenance engineering; Rechargeable batteries; State of charge; state-of-charge (SOC) alignment; Switches
• ISSN: 0278-0046; 1557-9948
• DOI: 10.1109/TIE.2024.3379639

For the maintenance of electric vehicle batteries, a special apparatus achieving the state-of-charge (SOC) alignment of the whole cells inside a battery pack is highly promising. Specifically, when battery packs are discharged to a safe SOC level before shipping, according to battery logistic policy, and charged back to a nominal SOC level before being replaced in the swapping station, the SOC levels of all cells should be aligned to a specific target level. Conventionally, numerous cell-balancing hardware architectures and control strategies are studied; however, they only equalize the SOC between cells, and a whole pack SOC alignment feature has not been evaluated. In this article, a novel algorithm with a coordinated operation between a pack-charger and cell-equalizer is proposed as a viable SOC alignment algorithm. The full-duplex coordinated strategy, which utilizes a bidirectional pack-charger and cell-equalizer, is proposed for alignment purposes, which can minimize the operating time and the energy loss. The theoretical strategy is investigated to achieve the minimal operation time, and the performance of the proposed method is verified by a hardware prototype for a battery pack with 20-series cells. After the alignment process, the cell SOC levels are equalized within a voltage deviation of 30 mV or SOC deviation of 3%, when the pack SOC level is simultaneously adjusted to a preset level. In comparison with the half-duplex strategy, the proposed strategy has a twice faster processing time, while the energy loss during the process is 38%, 10.4%, and 26.1% lower than before. Otherwise, the proposed strategy achieves higher speed of 52% and 28.9% compared with the conventional strategies in balancing speed comparison.