DR Loss-Free Dithering-Based Digital Background Linearity Calibration for SAR-Assisted Multi-Stage ADCs With Digital Input-Interference Cancellation

In this paper, we propose a correlation-based background linearity calibration technique to digitally correct the bit weights in successive approximation register (SAR)-assisted analog-to-digital converters (ADCs). Unlike typical dithering-based calibration techniques in which signal dynamic range (...

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Bibliographic Details
Published in:IEEE open journal of circuits and systems 2024, Vol.5, p.349-364
Main Authors: Zhang, Lizhen, Gao, Bo, Park, Kun-Woo, Edrian Lozada, Kent, Mabilangan, Raymond, Kim, Hyeongjin, Wu, Jianhui, Ryu, Seung-Tak
Format: Article
Language:English
Subjects:
Acceleration
Analog to digital converters
Analog-digital conversion
bit weight
Calibration
Codes
Convergence
convergence acceleration
Digital background calibration
dither injection
Dithering
Dynamic range
Engines
Gain
input-interference cancellation
Linearity
Noise levels
Pipelines
Redundancy
SAR-assisted ADC
Switches
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Description
Summary:In this paper, we propose a correlation-based background linearity calibration technique to digitally correct the bit weights in successive approximation register (SAR)-assisted analog-to-digital converters (ADCs). Unlike typical dithering-based calibration techniques in which signal dynamic range (DR) is unavoidably reduced, in this work, a small dither signal is injected into the input path by a simple switching scheme. The associated DR loss is avoided by the back-end redundancy. We also describe a capacitor-scanning dither method to accomplish simultaneous and independent identification of multiple bit weights. In addition, a digital-domain input-interference cancellation (IIC) technique is proposed to accelerate the convergence speed of the correlation-based calibration. The proposed calibration and acceleration techniques are analyzed by using both theoretical formulation and system simulation. The simulation results are presented with a 12-bit SAR-assisted two-stage pipeline ADC model. Owing to our proposed calibration, the spurious-free dynamic range (SFDR) increased from 60.1 to 84.8 dB and the signal to noise and distortion ratio (SNDR) improved from 55.4 to 72.5 dB. By comparing the cases with and without the proposed IIC technique, a 50\times reduction in convergence cycle could be achieved. The proposed calibration technique can be utilized to overcome the inherent DAC mismatch and residue gain errors to implement high-linearity ADCs, such as SAR-assisted ADCs in many different applications.
ISSN:2644-1225
2644-1225
DOI:10.1109/OJCAS.2024.3486809