Overvoltage Failure Process of Cascode GaN Field Effect Transistors

• Published in: Physica status solidi. A, Applications and materials science Applications and materials science, 2024-11, Vol.221 (21), p.n/a
• Main Authors: Saito, Wataru, Nishizawa, Shin‐ichi
• Format: Article
• Language: English
• Subjects: Avalanche transistors; breakdowns; Capacitance-voltage characteristics; cascode GaN FETs; Dielectric breakdown; Electron avalanche; Electron traps; Failure; Field effect transistors; Gallium nitrides; High electron mobility transistors; Overvoltage; overvoltage stresses; Semiconductor devices; Waveforms
• ISSN: 1862-6300; 1862-6319
• DOI: 10.1002/pssa.202300791

The failure process caused by overvoltage stress in cascode GaN–field effect transistors (FETs) is discussed through single unclamped inductive switching (UIS) waveforms, burst UIS waveforms, and capacitance–voltage characteristic shifts. One of the critical disadvantages of GaN–high electron mobility transistors (HEMTs) is their lack of UIS withstand capability, primarily because there is no mechanism for removing holes generated by avalanche breakdown. The device failure is observed at the drain voltage peak in the single UIS, and sudden and random breaks are observed in the burst UIS even with the same overvoltage stress. Both hole and electron traps after the burst UIS are observed, and the failure position is at the chip edge. From these results, it is verified that cascode GaN–FETs are broken due to time‐dependent dielectric breakdown of passivation films. The failure process caused by overvoltage stress in cascode GaN‐field effect transistors (FETs) is discussed through single and burst unclamped inductive switching waveforms. The device failure is observed at the drain voltage peak with sudden and random breaks at the chip edge. In these results, it is verified that cascode GaN‐FETs are broken due to time‐dependent dielectric breakdown of passivation films.