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Analyzing the operational versatility of advanced IBC solar cells at different temperatures and also with variation in minority carrier lifetimes

In this work, doped and dopant-free carrier-selective passivating contacts have been incorporated in Interdigitated Back Contact solar cells. TCAD simulation study was done to check the performance of an IBC-SHJ (Silicon Hetero-Junction) and IBC-POLO (POLy-silicon on Oxide as seen in TOPCon) cell st...

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Bibliographic Details
Published in:Journal of computational electronics 2024-12, Vol.23 (6), p.1170-1194
Main Authors: Acharyya, Shiladitya, Ghosh, Dibyendu Kumar, Banerjee, Dipali, Maity, Santanu
Format: Article
Language:English
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Summary:In this work, doped and dopant-free carrier-selective passivating contacts have been incorporated in Interdigitated Back Contact solar cells. TCAD simulation study was done to check the performance of an IBC-SHJ (Silicon Hetero-Junction) and IBC-POLO (POLy-silicon on Oxide as seen in TOPCon) cell structures for both p and n -type wafers. The IBC-POLO structure was also repeated with HfO 2 and ZrO 2 over electron transport and hole transport layers, respectively. Simulation study was done by replacing the doped silicon layers with dopant-free Transition Metal Oxides (TMOs). NiO was used as a dopant-free hole-selective contact, whereas Nb 2 O 5 was used a dopant-free electron-selective contact. The fabrication of these materials is non-hazardous and at low temperatures due to which they are preferable over the doped Si layers that require toxic gases like phosphine, diborane, etc. and may also require high temperatures. For example, poly-Si layer applied in IBC-POLO requires an annealing temperature of over 800 °C; similarly, the diffusion of Front Surface Field (FSF) layer in normal IBC cells also requires the same high temperature. Temperature variation was done on these structures to check the dependence of solar PV parameters of each IBC structure on different temperatures. Same variation was checked with minority carrier lifetime of the silicon wafer.
ISSN:1569-8025
1572-8137
DOI:10.1007/s10825-024-02232-y