A Compact Writing Scheme for the Reliability Challenges in 1T Multi-Level FeFET Array: Variation, Endurance, and Write Disturb

Multi-level cell (MLC) ferroelectric FETs (FeFETs) face critical reliability challenges including variation, endurance and write disturb. In this work, we proposed an innovative solution to tackle all the three challenges within a compact writing scheme. Combining error correction, endurance recover...

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Bibliographic Details
Published in:IEEE electron device letters 2024-01, Vol.45 (12), p.2387-2390
Main Authors: Zhou, Yuejia, Shao, Hanyong, Huang, Weiqin, Zhu, Runteng, Zhang, Yihan, Huang, Ru, Tang, Kechao
Format: Article
Language:English
Subjects:
Arrays
Circuit reliability
Costs
Endurance
endurance recovery
Error correction
FeFETs
Multi-level cell (MLC) FeFET
Performance evaluation
Reliability
variation
Workflow
write disturb
Writing
writing scheme
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Summary:Multi-level cell (MLC) ferroelectric FETs (FeFETs) face critical reliability challenges including variation, endurance and write disturb. In this work, we proposed an innovative solution to tackle all the three challenges within a compact writing scheme. Combining error correction, endurance recovery, and self-compensated writing, the proposed scheme achieves a \gt 6\times reduction in error ratio (ER), a >100 improvement in endurance, and a \gt 7\times reduction in Vth shift. Reliable 2 bits/cell storage with high endurance of 10^{{8}} cycles and write-disturb immunity is experimentally demonstrated in the fabricated 1T FeFET array. This writing scheme is realized within a single work flow, and can be readily implemented in the operation circuits.
ISSN:0741-3106
1558-0563
DOI:10.1109/LED.2024.3485803