FPGA implementation of the HL-LHC CMS Drift Tubes Level-1 Trigger algorithm

The High-Luminosity Large Hadron Collider (HL-LHC) has motivated a generalized upgrade in electronic systems across all experiments. In the new electronics architecture for the CMS (Compact Muon Solenoid) Drift Tubes detector, the trigger generation moves from on-detector ASICs to the back-end, to b...

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Bibliographic Details
Published in:Journal of instrumentation 2025-01, Vol.20 (1), p.C01024
Main Authors: Navarro-Tobar, A., León Holgado, J.
Format: Article
Language:English
Subjects:
Algorithms
Digital electronic circuits
Drift tubes
Electron tubes
Electronic systems
Large Hadron Collider
Luminosity
Muons
Solenoids
Trigger algorithms
Trigger concepts and systems (hardware and software)
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Summary:The High-Luminosity Large Hadron Collider (HL-LHC) has motivated a generalized upgrade in electronic systems across all experiments. In the new electronics architecture for the CMS (Compact Muon Solenoid) Drift Tubes detector, the trigger generation moves from on-detector ASICs to the back-end, to be carried out by top-range FPGAs. The new algorithm aims to deliver full-resolution, offline-grade performance in the reconstruction of muon segments. To achieve this objective, meeting the latency and data rate requirements, a high-speed, highly-pipelined FPGA design with several optimizations has been developed. This work describes the architecture and performance of this algorithm, as well as the challenges encountered during implementation and the solutions adopted.
ISSN:1748-0221
1748-0221
DOI:10.1088/1748-0221/20/01/C01024