A Low-Cost BIST Architecture for Linear Histogram Testing of ADCs

This paper investigates the viability of an ADC BIST scheme for implementing the histogram test technique. An original approach is developed to extract the ADC parameters from the histogram with a minimum area overhead. In particular, it is shown that the choice of a triangle-wave input signal combi...

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Bibliographic Details
Published in:Journal of electronic testing 2001-04, Vol.17 (2), p.139
Main Authors: Azaïs, F, Bernard, S, Bertrand, Y, Renovell, M
Format: Article
Language:English
Subjects:
Circuits
Semiconductors
Tests
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Summary:This paper investigates the viability of an ADC BIST scheme for implementing the histogram test technique. An original approach is developed to extract the ADC parameters from the histogram with a minimum area overhead. In particular, it is shown that the choice of a triangle-wave input signal combined with an appropriate time decomposition technique of the test procedure permits to drastically reduce the required on-chip hardware circuitry.[PUBLICATION ABSTRACT]
ISSN:0923-8174
1573-0727
DOI:10.1023/A:1011173710479