A Built-in Self-Test Scheme with Diagnostics Support for Embedded SRAM

In this paper we propose a novel built-in self-test (BIST) design for embedded SRAM cores. Our contribution includes a compact and efficient BIST circuit with diagnosis support and an automatic diagnostic system. The diagnosis module of our BIST circuit can capture the error syndromes as well as fau...

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Bibliographic Details
Published in:Journal of electronic testing 2002-12, Vol.18 (6), p.637
Main Authors: Wang, Chih-wea, Wu, Chi-feng, Li, Jin-fu, Wu, Cheng-wen, Teng, Tony, Chiu, Kevin, Lin, Hsiao-ping
Format: Article
Language:English
Subjects:
Failure analysis
Studies
Online Access:Get full text
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Summary:In this paper we propose a novel built-in self-test (BIST) design for embedded SRAM cores. Our contribution includes a compact and efficient BIST circuit with diagnosis support and an automatic diagnostic system. The diagnosis module of our BIST circuit can capture the error syndromes as well as fault locations for the purposes of repair and fault/failure analysis. In addition, our design provides programmability for custom March algorithms with lower hardware cost. The combination of the on-line programming mode and diagnostic system dramatically reduces the effort in design debugging and yield enhancement. We have designed and implemented test chips with our BIST design. Experimental results show that the area overhead of the proposed BIST design is only 2.4% for a 128 KB SRAM, and 0.65% for a 2 MB one.[PUBLICATION ABSTRACT]
ISSN:0923-8174
1573-0727
DOI:10.1023/A:1020805224219