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Characteristics of n-Channel MOSFETs With Tailored Source/Drain Extension for Mask ROM and EEPROM Applications
A novel 2-bits-per-transistor mask-programmable read-only memory (mask ROM) device with gate-to-drain nonoverlapped implantation (NOI) is investigated in this paper. The NOI mask ROM can be coded by using the lightly doped drain implantation mask and related processes. This simple coding scheme is f...
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Published in: | IEEE transactions on electron devices 2009-09, Vol.56 (9), p.2099-2106 |
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Main Authors: | , , , , |
Format: | Article |
Language: | English |
Subjects: | |
Citations: | Items that this one cites Items that cite this one |
Online Access: | Get full text |
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Summary: | A novel 2-bits-per-transistor mask-programmable read-only memory (mask ROM) device with gate-to-drain nonoverlapped implantation (NOI) is investigated in this paper. The NOI mask ROM can be coded by using the lightly doped drain implantation mask and related processes. This simple coding scheme is fully compatible with industrial CMOS processing. The measured threshold voltage difference DeltaV th between the two logic states (ldquo0rdquo and ldquo1rdquo) of the devices is approximately 0.6 V. Moreover, DeltaV th can be improved when the pocket implant is incorporated into the NOI region based on the device simulation. The characteristics of this NOI mask ROM, including 2-bits-per-transistor operation, body effects, hot carrier impact, and array layouts, are investigated. By sharing the same array layout and readout circuit, the potential of NOI devices' seamless migration between the mask ROM and electrically erasable programmable read-only memory functions are also demonstrated. |
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ISSN: | 0018-9383 1557-9646 |
DOI: | 10.1109/TED.2009.2026521 |