Characteristics of n-Channel MOSFETs With Tailored Source/Drain Extension for Mask ROM and EEPROM Applications

• Published in: IEEE transactions on electron devices 2009-09, Vol.56 (9), p.2099-2106
• Main Authors: Yuan-Feng Chen, Jeng Gong, Wei-Jen Tung, Shang-Wei Chou, Jeng, E.S.
• Format: Article
• Language: English
• Subjects: Applied sciences; Arrays; Design. Technologies. Operation analysis. Testing; Devices; Drains; Electrically erasable; Electrically erasable programmable read-only memory (EEPROM); Electronics; EPROM; Exact sciences and technology; Implantation; Integrated circuits; Integrated circuits by function (including memories and processors); Logic; Logic gates; mask-programmable read-only memory (mask ROM); Masks; MOSFET circuits; nonoverlapped implantation (NOI); Nonvolatile memory; nonvolatile memory (NVM); Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Silicon compounds; Threshold voltage; Transistors
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/TED.2009.2026521

A novel 2-bits-per-transistor mask-programmable read-only memory (mask ROM) device with gate-to-drain nonoverlapped implantation (NOI) is investigated in this paper. The NOI mask ROM can be coded by using the lightly doped drain implantation mask and related processes. This simple coding scheme is fully compatible with industrial CMOS processing. The measured threshold voltage difference DeltaV th between the two logic states (ldquo0rdquo and ldquo1rdquo) of the devices is approximately 0.6 V. Moreover, DeltaV th can be improved when the pocket implant is incorporated into the NOI region based on the device simulation. The characteristics of this NOI mask ROM, including 2-bits-per-transistor operation, body effects, hot carrier impact, and array layouts, are investigated. By sharing the same array layout and readout circuit, the potential of NOI devices' seamless migration between the mask ROM and electrically erasable programmable read-only memory functions are also demonstrated.