Pipeline Architectures for Radix-2 New Mersenne Number Transform

Number theoretic transforms which operate in rings or fields of integers and use modular arithmetic operations can perform operations of convolution and correlation very efficiently and without round-off errors; thus, they are well matched to the implementation of digital filters. One such transform...

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Bibliographic Details
Published in:IEEE transactions on circuits and systems. I, Regular papers Regular papers, 2009-08, Vol.56 (8), p.1668-1680
Main Authors: Nibouche, O., Boussakta, S., Darnell, M.
Format: Article
Language:English
Subjects:
Architecture
Arithmetic
Convolution
Correlation
Digital arithmetic
Digital filters
Fast Fourier transforms
Field programmable gate arrays
Format
Kernel
Modular
New Mersenne number transform (NMNT)
number theoretic transform (NTT)
pipeline architectures
Pipelines
Roundoff errors
Studies
Throughput
Transforms
Very high speed integrated circuits
VHDL
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Summary:Number theoretic transforms which operate in rings or fields of integers and use modular arithmetic operations can perform operations of convolution and correlation very efficiently and without round-off errors; thus, they are well matched to the implementation of digital filters. One such transform is the new Mersenne number transform, which relaxes the rigid relationship between the length of the transform and the wordlength in Fermat and Mersenne number transforms where the kernel is usually equal to a power of two. In this paper, three novel pipeline architectures that implement this transform are presented. The proposed architectures are scalable, parameterized, and can be easily pipelined; they are thus ideally suited to very high speed integrated circuit hardware-description-language (VHDL) descriptions. These architectures process data sequentially and have either one or two inputs and two or four outputs. The different input and output formats have resulted in the proposed architectures having different performances in terms of processing time and area requirements. Furthermore, they give the designer more choices in meeting the requirements of the application being implemented. A field-programmable gate array (FPGA) implementation of the proposed architectures has demonstrated that a throughput rate of up to 6.09 Gbit/s can be achieved for a 1024-sample transform, with samples coded to 31 bits.
ISSN:1549-8328
1558-0806
DOI:10.1109/TCSI.2008.2008266