Multilevel Multiphase Space Vector PWM Algorithm

In the last few years, interest in multiphase converter technology has increased due to the benefits of using more than three phases in drive applications. Besides, multilevel converter technology permits the achievement of high power ratings with voltage limited devices. Multilevel multiphase techn...

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Bibliographic Details
Published in:IEEE transactions on industrial electronics (1982) 2008-05, Vol.55 (5), p.1933-1942
Main Authors: Lopez, O., Alvarez, J., Doval-Gandoy, J., Freijedo, F.D.
Format: Article
Language:English
Subjects:
Algorithms
Computational complexity
Converters
Electric potential
Field programmable gate arrays
Field-programmable gate array (FPGA)
Hardware
Mathematical analysis
Modulation
modulation algorithm
Multilevel
multilevel multiphase converter
Multiphase
Pulse duration modulation
Pulse modulation
Pulse width modulation converters
Space technology
Space vector pulse width modulation
space vector pulsewidth modulation (SVPWM)
Studies
Testing
Topology
Voltage
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Summary:In the last few years, interest in multiphase converter technology has increased due to the benefits of using more than three phases in drive applications. Besides, multilevel converter technology permits the achievement of high power ratings with voltage limited devices. Multilevel multiphase technology combines the benefits of both technologies, but new modulation techniques must be developed in order to take advantage of multilevel multiphase converters. In this paper, a novel space vector pulsewidth modulation (SVPWM) algorithm for multilevel multiphase voltage source converters is presented. This algorithm is the result of the two main contributions of this paper: the demonstration that a multilevel multiphase modulator can be realized from a two-level multiphase modulator, and the development of a new two-level multiphase SVPWM algorithm. The multiphase SVPWM algorithm presented in this paper can be applied to most multilevel topologies; it has low computational complexity and it is suitable for hardware implementations. Finally, the algorithm was implemented in a low-cost field-programmable gate array and it was tested in a laboratory with a real prototype using a five-level five-phase inverter.
ISSN:0278-0046
1557-9948
DOI:10.1109/TIE.2008.918466