Development of Single-Transistor-Control LDO Based on Flipped Voltage Follower for SoC

The design issues of a single-transistor-control (STC) low-drop-out (LDO) based on flipped voltage follower is discussed in this paper, in particular the feedback stability at different conditions of output capacitors, equivalent series resistances (ESRs) and load current. Based on the analysis, an...

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Bibliographic Details
Published in:IEEE transactions on circuits and systems. I, Regular papers Regular papers, 2008-06, Vol.55 (5), p.1392-1401
Main Authors: Tsz Yin Man, Ka Nang Leung, Chi Yat Leung, Mok, P.K.T., Mansun Chan
Format: Article
Language:English
Subjects:
Capacitors
Circuit stability
Circuits
CMOS technology
Control
Electric potential
Equivalence
Flipped voltage follower (FVF)
Followers
Grounds
Impedance
loop gain and power management
low drop out (LDO)
Low voltage
Output feedback
Paramagnetic resonance
Power system management
Transient response
Voltage
Voltage control
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Summary:The design issues of a single-transistor-control (STC) low-drop-out (LDO) based on flipped voltage follower is discussed in this paper, in particular the feedback stability at different conditions of output capacitors, equivalent series resistances (ESRs) and load current. Based on the analysis, an STC LDO was implemented in a standard 0.35-mum MOS technology. It is proven experimentally that the LDO provides stable voltage regulation at a variety of output-capacitor/ESR conditions and is also stable in no output capacitor condition. The preset output voltage, minimum unregulated input voltage, maximum output current at a dropout voltage of 200 mV, ground current and active chip area are 1 V, 1.2 V, 50 mA, 95 muA, and 140 mum times 320 mum, respectively. The full-load transient response in the no output capacitor case is faster than a micro second and is about 300 ns.
ISSN:1549-8328
1558-0806
DOI:10.1109/TCSI.2008.916568