A Modified IBIS Model Aimed at Signal Integrity Analysis of Systems in Package

Input-output buffer information specification BIS (IBIS) models are descriptions of the output buffers, used by the printed circuit board (PCB) designer to evaluate the integrity and the quality of the signals. The extension of the use of IBIS models to the system in package (SiP) world is considere...

Full description

Saved in:
Bibliographic Details
Published in:IEEE transactions on circuits and systems. I, Regular papers Regular papers, 2008-08, Vol.55 (7), p.1921-1928
Main Authors: Pulici, P., Girardi, A., Vanalli, G.P., Izzi, R., Bernardi, G., Ripamonti, G., Strollo, A., Campardo, G.
Format: Article
Language:English
Subjects:
Buffer circuits
Buffers
Circuit boards
circuit modeling
Circuit simulation
Computer simulation
Crosstalk
Descriptions
driver circuits
Electric potential
electromagnetic interferences
Information analysis
Integrated circuit modeling
Integrated circuit packaging
interconnections
Mathematical models
Packages
Printed circuits
Signal analysis
Signal design
Voltage
Wire
Citations: Items that this one cites
Items that cite this one
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:Input-output buffer information specification BIS (IBIS) models are descriptions of the output buffers, used by the printed circuit board (PCB) designer to evaluate the integrity and the quality of the signals. The extension of the use of IBIS models to the system in package (SiP) world is considered. It is found that IBIS models demonstrate some limits for this application, mainly due to the poor stabilization of the supply voltage rails. An example highlighting the IBIS model limits is given. A simple hand analysis of the phenomenon is performed, from which we derive a simple solution to the problem, consisting in an improvement of the structure of the IBIS model. Simulations run making use of the improved models show a much better accuracy of the signal shapes, within 5% of the simulations run with a state-of-the-art transistor level description of the buffers.
ISSN:1549-8328
1558-0806
DOI:10.1109/TCSI.2008.918203